Robustness analysis of watermark verification techniques for FPGA netlist cores

Daniel Ziener*, Moritz Schmid, Jürgen Teich

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review


In this paper we analyze the robustness of watermarking techniques for FPGA IP cores against attacks. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. For robustness analysis we enhanced a theoretical watermarking model, originally introduced for multimedia watermarking. Finally, two exemplary watermarking techniques for netlist cores using different verification strategies are described and the robustness against attacks is analyzed.

Original languageEnglish
Title of host publicationDesign Methodologies for Secure Embedded Systems
Subtitle of host publicationFestschrift in Honor of Prof. Dr.-Ing. Sorin A. Huss
EditorsAlexander Biedermann, H. Gregor Molter
Number of pages23
Publication statusPublished - 2010
Externally publishedYes

Publication series

NameLecture Notes in Electrical Engineering
ISSN (Print)18761100
ISSN (Electronic)18761119


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