Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

Lodewijk T. Smit; Gerard J.M. Smit; Johann L. Hurink; Hajo Broersma; Daniël Paulusma; Pascal T. Wolkotte

doi:10.1109/FPT.2004.1393315

Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

Lodewijk T. Smit, Gerard J.M. Smit, Johann L. Hurink, Hajo Broersma, Daniël Paulusma, Pascal T. Wolkotte

Discrete Mathematics and Mathematical Programming

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

33 Citations (Scopus)

49 Downloads (Pure)

Abstract

This paper evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled System on Chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate Quality of Service (QoS). A realistic example is mapped using this algorithm.

Original language	English
Title of host publication	2004 IEEE International Conference on Field-Programmable Technology, 2004
Subtitle of host publication	Proceedings
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	421-424
Number of pages	4
ISBN (Print)	0-7803-8651-5
DOIs	https://doi.org/10.1109/FPT.2004.1393315
Publication status	Published - Dec 2004
Event	2004 IEEE International Conference on Field-Programmable Technology, FPT 2004 - Brisbane, Australia Duration: 6 Dec 2004 → 8 Dec 2004

Conference

Conference	2004 IEEE International Conference on Field-Programmable Technology, FPT 2004
Abbreviated title	FPT
Country/Territory	Australia
City	Brisbane
Period	6/12/04 → 8/12/04

Keywords

CAES-EEA: Efficient Embedded Architectures
EWI-1485
IR-48501
EC Grant Agreement nr.: FP6/001908
METIS-220029

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10.1109/FPT.2004.1393315

Smit2004run-timeAccepted author version, 138 KB

Cite this

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title = "Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture",

abstract = "This paper evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled System on Chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate Quality of Service (QoS). A realistic example is mapped using this algorithm.",

keywords = "CAES-EEA: Efficient Embedded Architectures, EWI-1485, IR-48501, EC Grant Agreement nr.: FP6/001908, METIS-220029",

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note = "Imported from CHAMELEON.xml; 2004 IEEE International Conference on Field-Programmable Technology, FPT 2004, FPT ; Conference date: 06-12-2004 Through 08-12-2004",

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Smit, LT, Smit, GJM, Hurink, JL , Broersma, H, Paulusma, D & Wolkotte, PT 2004, Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture. in 2004 IEEE International Conference on Field-Programmable Technology, 2004: Proceedings. IEEE, Piscataway, NJ, pp. 421-424, 2004 IEEE International Conference on Field-Programmable Technology, FPT 2004, Brisbane, Queensland, Australia, 6/12/04. https://doi.org/10.1109/FPT.2004.1393315

Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture. / Smit, Lodewijk T.; Smit, Gerard J.M.; Hurink, Johann L. et al.
2004 IEEE International Conference on Field-Programmable Technology, 2004: Proceedings. Piscataway, NJ: IEEE, 2004. p. 421-424.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Smit, Lodewijk T.

AU - Smit, Gerard J.M.

AU - Hurink, Johann L.

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AU - Paulusma, Daniël

AU - Wolkotte, Pascal T.

N1 - Imported from CHAMELEON.xml

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N2 - This paper evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled System on Chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate Quality of Service (QoS). A realistic example is mapped using this algorithm.

AB - This paper evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled System on Chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate Quality of Service (QoS). A realistic example is mapped using this algorithm.

KW - CAES-EEA: Efficient Embedded Architectures

KW - EWI-1485

KW - IR-48501

KW - EC Grant Agreement nr.: FP6/001908

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Y2 - 6 December 2004 through 8 December 2004

ER -

Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

Abstract

Conference

Keywords

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