This paper presents an iterative hierarchical approach to map an application to a parallel heterogeneous SoC architecture at run-time. The application is modeled as a set of communicating processes. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service. This approach is flexible, scalable and the performance looks promising.
|Conference||International Symposium on System-on-Chip, SoC 2006|
|Period||13/11/05 → 16/11/05|
|Other||13-16 November 2005|
- EC Grant Agreement nr.: FP6/001908
- CAES-EEA: Efficient Embedded Architectures