Run-time Mapping of Applications to a Heterogeneous SoC

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Abstract

This paper presents an iterative hierarchical approach to map an application to a parallel heterogeneous SoC architecture at run-time. The application is modeled as a set of communicating processes. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service. This approach is flexible, scalable and the performance looks promising.
Original languageUndefined
Title of host publication2005 International Symposium on System-on-Chip Proceedings
PublisherIEEE Computer Society
Pages78-81
Number of pages4
ISBN (Print)0-7803-9294-9
DOIs
Publication statusPublished - Nov 2005
EventInternational Symposium on System-on-Chip, SoC 2006 - Tampere, Finland
Duration: 13 Nov 200516 Nov 2005

Publication series

Name
PublisherIEEE

Conference

ConferenceInternational Symposium on System-on-Chip, SoC 2006
Period13/11/0516/11/05
Other13-16 November 2005

Keywords

  • EC Grant Agreement nr.: FP6/001908
  • EWI-1468
  • IR-54767
  • METIS-229233
  • CAES-EEA: Efficient Embedded Architectures

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