Abstract
This paper presents an iterative hierarchical approach to map an application to a parallel heterogeneous SoC architecture at run-time. The application is modeled as a set of communicating processes. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service. This approach is flexible, scalable and the performance looks promising.
| Original language | Undefined |
|---|---|
| Title of host publication | 2005 International Symposium on System-on-Chip Proceedings |
| Publisher | IEEE Computer Society |
| Pages | 78-81 |
| Number of pages | 4 |
| ISBN (Print) | 0-7803-9294-9 |
| DOIs | |
| Publication status | Published - Nov 2005 |
Publication series
| Name | |
|---|---|
| Publisher | IEEE |
Keywords
- EC Grant Agreement nr.: FP6/001908
- EWI-1468
- IR-54767
- METIS-229233
- CAES-EEA: Efficient Embedded Architectures
Cite this
Smit, L. T., Hurink, J. L., & Smit, G. J. M. (2005). Run-time Mapping of Applications to a Heterogeneous SoC. In 2005 International Symposium on System-on-Chip Proceedings (pp. 78-81). IEEE Computer Society. https://doi.org/10.1109/ISSOC.2005.1595649