Sampling phase lock loop (PLL) with low power clock buffer

X. Gao (Inventor), A. Bahai (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), G. Socci (Inventor)

    Research output: Patent

    33 Downloads (Pure)

    Abstract

    A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.
    Original languageUndefined
    Patent numberUS8427209B2
    Priority date20/12/10
    Publication statusPublished - 23 Apr 2013

    Keywords

    • METIS-297737
    • IR-86700
    • EWI-23523

    Cite this

    Gao, X., Bahai, A., Bohsali, M., Djabbari, A., Klumperink, E. A. M., Nauta, B., & Socci, G. (2013). Sampling phase lock loop (PLL) with low power clock buffer. (Patent No. US8427209B2).
    Gao, X. (Inventor) ; Bahai, A. (Inventor) ; Bohsali, M. (Inventor) ; Djabbari, A. (Inventor) ; Klumperink, Eric A.M. (Inventor) ; Nauta, Bram (Inventor) ; Socci, G. (Inventor). / Sampling phase lock loop (PLL) with low power clock buffer. Patent No.: US8427209B2.
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    abstract = "A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.",
    keywords = "METIS-297737, IR-86700, EWI-23523",
    author = "X. Gao and A. Bahai and M. Bohsali and A. Djabbari and Klumperink, {Eric A.M.} and Bram Nauta and G. Socci",
    year = "2013",
    month = "4",
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    Gao, X, Bahai, A, Bohsali, M, Djabbari, A, Klumperink, EAM, Nauta, B & Socci, G 2013, Sampling phase lock loop (PLL) with low power clock buffer, Patent No. US8427209B2.

    Sampling phase lock loop (PLL) with low power clock buffer. / Gao, X. (Inventor); Bahai, A. (Inventor); Bohsali, M. (Inventor); Djabbari, A. (Inventor); Klumperink, Eric A.M. (Inventor); Nauta, Bram (Inventor); Socci, G. (Inventor).

    Patent No.: US8427209B2.

    Research output: Patent

    TY - PAT

    T1 - Sampling phase lock loop (PLL) with low power clock buffer

    AU - Gao, X.

    AU - Bahai, A.

    AU - Bohsali, M.

    AU - Djabbari, A.

    AU - Klumperink, Eric A.M.

    AU - Nauta, Bram

    AU - Socci, G.

    PY - 2013/4/23

    Y1 - 2013/4/23

    N2 - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

    AB - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

    KW - METIS-297737

    KW - IR-86700

    KW - EWI-23523

    UR - https://www.google.com/patents/US8427209?dq=ininventor:gao+klumperink+nauta&hl=en&sa=X&ei=zNS6UaSQFcftOsLggeAP&ved=0CEMQ6AEwAg

    M3 - Patent

    M1 - US8427209B2

    ER -

    Gao X, Bahai A, Bohsali M, Djabbari A, Klumperink EAM, Nauta B et al, inventors. Sampling phase lock loop (PLL) with low power clock buffer. US8427209B2. 2013 Apr 23.