Sampling phase lock loop (PLL) with low power clock buffer

X. Gao; A. Bahai; M. Bohsali; A. Djabbari; Eric A.M. Klumperink; Bram Nauta; G. Socci

Sampling phase lock loop (PLL) with low power clock buffer

X. Gao (Inventor), A. Bahai (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), G. Socci (Inventor)

Research output: Patent

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Abstract

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Original language	Undefined
Patent number	US8427209B2
Priority date	20/12/10
Publication status	Published - 23 Apr 2013

Keywords

METIS-297737
IR-86700
EWI-23523

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http://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=8427209B2&KC=B2&FT=D&ND=5&date=20130423&DB=worldwide.espacenet.com&locale=en_EP

Cite this

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title = "Sampling phase lock loop (PLL) with low power clock buffer",

abstract = "A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.",

keywords = "METIS-297737, IR-86700, EWI-23523",

author = "X. Gao and A. Bahai and M. Bohsali and A. Djabbari and Klumperink, {Eric A.M.} and Bram Nauta and G. Socci",

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TY - PAT

T1 - Sampling phase lock loop (PLL) with low power clock buffer

AU - Gao, X.

AU - Bahai, A.

AU - Bohsali, M.

AU - Djabbari, A.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Socci, G.

PY - 2013/4/23

Y1 - 2013/4/23

N2 - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

AB - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

KW - METIS-297737

KW - IR-86700

KW - EWI-23523

UR - https://www.google.com/patents/US8427209?dq=ininventor:gao+klumperink+nauta&hl=en&sa=X&ei=zNS6UaSQFcftOsLggeAP&ved=0CEMQ6AEwAg

M3 - Patent

M1 - US8427209B2

ER -

Sampling phase lock loop (PLL) with low power clock buffer

Abstract

Keywords

Access to Document

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Research output

Sampling phase lock loop (PLL) with low power clock buffer

Cite this