Sampling phase lock loop (PLL) with low power clock buffer

X. Gao (Inventor), A. Bahai (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), G. Socci (Inventor)

    Research output: Patent

    34 Downloads (Pure)

    Abstract

    A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.
    Original languageUndefined
    Patent numberUS8427209B2
    Priority date20/12/10
    Publication statusPublished - 23 Apr 2013

    Keywords

    • METIS-297737
    • IR-86700
    • EWI-23523

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