Sampling phase lock loop (PLL) with low power clock buffer

X. Gao; A. Bahai; M. Bohsali; A. Djabbari; Eric A.M. Klumperink; Bram Nauta; G. Socci

Sampling phase lock loop (PLL) with low power clock buffer

X. Gao (Inventor), A. Bahai (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), G. Socci (Inventor)

Research output: Patent

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Abstract

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Original language	Undefined
Patent number	US 2013/0038365 A1
Priority date	17/10/12
Publication status	Published - 14 Feb 2013

Keywords

METIS-297695
EWI-23431

Access to Document

US2013038365A1

http://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=2013038365A1&KC=A1&FT=D&ND=6&date=20130214&DB=worldwide.espacenet.com&locale=en_EP

Cite this

@misc{4bbce974f5e5404a981447c28b98fd72,

title = "Sampling phase lock loop (PLL) with low power clock buffer",

abstract = "A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.",

keywords = "METIS-297695, EWI-23431",

author = "X. Gao and A. Bahai and M. Bohsali and A. Djabbari and Klumperink, {Eric A.M.} and Bram Nauta and G. Socci",

year = "2013",

month = feb,

day = "14",

language = "Undefined",

type = "Patent",

note = "US 2013/0038365 A1",

}

TY - PAT

T1 - Sampling phase lock loop (PLL) with low power clock buffer

AU - Gao, X.

AU - Bahai, A.

AU - Bohsali, M.

AU - Djabbari, A.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Socci, G.

PY - 2013/2/14

Y1 - 2013/2/14

N2 - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

AB - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

KW - METIS-297695

KW - EWI-23431

M3 - Patent

M1 - US 2013/0038365 A1

ER -