Abstract
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.
Original language | Undefined |
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Patent number | US 2013/0038365 A1 |
Priority date | 17/10/12 |
Publication status | Published - 14 Feb 2013 |
Keywords
- METIS-297695
- EWI-23431