Sampling phase lock loop (PLL) with low power clock buffer

X. Gao; A. Bahai; M. Bohsali; A. Djabbari; Eric A.M. Klumperink; Bram Nauta; G. Socci

Sampling phase lock loop (PLL) with low power clock buffer

X. Gao (Inventor), A. Bahai (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), G. Socci (Inventor)

Research output: Patent

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Abstract

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Original language	Undefined
Patent number	US 2013/0038365 A1
Priority date	17/10/12
Publication status	Published - 14 Feb 2013

Keywords

METIS-297695
EWI-23431

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US2013038365A1

http://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=2013038365A1&KC=A1&FT=D&ND=6&date=20130214&DB=worldwide.espacenet.com&locale=en_EP

1 Patent

Sampling phase lock loop (PLL) with low power clock buffer
Gao, X., Bahai, A., Bohsali, M., Djabbari, A., Klumperink, E. A. M., Nauta, B. & Socci, G., 23 Apr 2013, Patent No. US8427209B2, Priority date 20 Dec 2010
Research output: Patent

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Cite this

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abstract = "A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.",

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AU - Gao, X.

AU - Bahai, A.

AU - Bohsali, M.

AU - Djabbari, A.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Socci, G.

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AB - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

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KW - EWI-23431

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