Sampling phase lock loop (PLL) with low power clock buffer

X. Gao (Inventor), A. Bahai (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), G. Socci (Inventor)

    Research output: Patent

    87 Downloads (Pure)

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