Scan cell design for enhanced delay fault testability

G. van Brakel, Y. Xing, H.G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    Abstract

    Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell
    Original languageEnglish
    Title of host publicationProceedings IEEE ASIC'92
    Place of PublicationRochester, NY
    PublisherIEEE
    Pages372-375
    Number of pages0
    ISBN (Print)9780780307681
    DOIs
    Publication statusPublished - 1 Sept 1992
    Event5th Annual IEEE International ASIC Conference and Exhibit - Rochester, United States
    Duration: 21 Sept 199225 Sept 1992
    Conference number: 5

    Other

    Other5th Annual IEEE International ASIC Conference and Exhibit
    Country/TerritoryUnited States
    CityRochester
    Period21/09/9225/09/92

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