Scan cell design for enhanced delay fault testability

Gerrit van Brakel; G. van Brakel; Yizi Xing; Y. Xing; Hans G. Kerkhoff

doi:10.1109/ASIC.1992.270266

Scan cell design for enhanced delay fault testability

Gerrit van Brakel, G. van Brakel, Yizi Xing, Y. Xing, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell

Original language	Undefined
Title of host publication	Proceedings IEEE ASIC'92
Place of Publication	Rochester, NY
Publisher	IEEE
Pages	372-375
Number of pages	0
ISBN (Print)	9780780307681
DOIs	https://doi.org/10.1109/ASIC.1992.270266
Publication status	Published - 1 Sep 1992
Event	Fifth Annual IEEE International ASIC Conference and Exhibit - Rochester, NY Duration: 21 Sep 1992 → 25 Sep 1992

Publication series

Name
Publisher	IEEE

Other

Other	Fifth Annual IEEE International ASIC Conference and Exhibit
Period	21/09/92 → 25/09/92
Other	September 21-25, 1992

Keywords

METIS-112958
IR-16074

Access to Document

10.1109/ASIC.1992.270266

Brakel92scan

Cite this

@inproceedings{df771bc3de1b45f3b9df3d343ac9fbe9,

title = "Scan cell design for enhanced delay fault testability",

abstract = "Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell",

keywords = "METIS-112958, IR-16074",

author = "{van Brakel}, Gerrit and {van Brakel}, G. and Yizi Xing and Y. Xing and Kerkhoff, {Hans G.}",

year = "1992",

month = sep,

day = "1",

doi = "10.1109/ASIC.1992.270266",

language = "Undefined",

isbn = "9780780307681",

publisher = "IEEE",

pages = "372--375",

booktitle = "Proceedings IEEE ASIC'92",

address = "United States",

note = "null ; Conference date: 21-09-1992 Through 25-09-1992",

}

TY - GEN

T1 - Scan cell design for enhanced delay fault testability

AU - van Brakel, Gerrit

AU - van Brakel, G.

AU - Xing, Yizi

AU - Xing, Y.

AU - Kerkhoff, Hans G.

PY - 1992/9/1

Y1 - 1992/9/1

N2 - Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell

AB - Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell

KW - METIS-112958

KW - IR-16074

U2 - 10.1109/ASIC.1992.270266

DO - 10.1109/ASIC.1992.270266

M3 - Conference contribution

SN - 9780780307681

SP - 372

EP - 375

BT - Proceedings IEEE ASIC'92

PB - IEEE

CY - Rochester, NY

Y2 - 21 September 1992 through 25 September 1992

ER -