Abstract
Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell
Original language | English |
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Title of host publication | Proceedings IEEE ASIC'92 |
Place of Publication | Rochester, NY |
Publisher | IEEE |
Pages | 372-375 |
Number of pages | 0 |
ISBN (Print) | 9780780307681 |
DOIs | |
Publication status | Published - 1 Sept 1992 |
Event | 5th Annual IEEE International ASIC Conference and Exhibit - Rochester, United States Duration: 21 Sept 1992 → 25 Sept 1992 Conference number: 5 |
Other
Other | 5th Annual IEEE International ASIC Conference and Exhibit |
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Country/Territory | United States |
City | Rochester |
Period | 21/09/92 → 25/09/92 |