Scan cell design for enhanced delay fault testability

G. van Brakel; Y. Xing; H.G. Kerkhoff

doi:10.1109/ASIC.1992.270266

Scan cell design for enhanced delay fault testability

G. van Brakel, Y. Xing, H.G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

139 Downloads (Pure)

Abstract

Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell

Original language	English
Title of host publication	Proceedings IEEE ASIC'92
Place of Publication	Rochester, NY
Publisher	IEEE
Pages	372-375
Number of pages	0
ISBN (Print)	9780780307681
DOIs	https://doi.org/10.1109/ASIC.1992.270266
Publication status	Published - 1 Sept 1992
Event	5th Annual IEEE International ASIC Conference and Exhibit - Rochester, United States Duration: 21 Sept 1992 → 25 Sept 1992 Conference number: 5

Other

Other	5th Annual IEEE International ASIC Conference and Exhibit
Country/Territory	United States
City	Rochester
Period	21/09/92 → 25/09/92

Access to Document

10.1109/ASIC.1992.270266

ArticleFinal published version, 362 KB

Cite this

@inproceedings{df771bc3de1b45f3b9df3d343ac9fbe9,

title = "Scan cell design for enhanced delay fault testability",

abstract = "Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell",

author = "{van Brakel}, G. and Y. Xing and H.G. Kerkhoff",

year = "1992",

month = sep,

day = "1",

doi = "10.1109/ASIC.1992.270266",

language = "English",

isbn = "9780780307681",

pages = "372--375",

booktitle = "Proceedings IEEE ASIC'92",

publisher = "IEEE",

address = "United States",

note = "5th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 21-09-1992 Through 25-09-1992",

}

TY - GEN

T1 - Scan cell design for enhanced delay fault testability

AU - van Brakel, G.

AU - Xing, Y.

AU - Kerkhoff, H.G.

N1 - Conference code: 5

PY - 1992/9/1

Y1 - 1992/9/1

N2 - Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell

AB - Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell

U2 - 10.1109/ASIC.1992.270266

DO - 10.1109/ASIC.1992.270266

M3 - Conference contribution

SN - 9780780307681

SP - 372

EP - 375

BT - Proceedings IEEE ASIC'92

PB - IEEE

CY - Rochester, NY

T2 - 5th Annual IEEE International ASIC Conference and Exhibit

Y2 - 21 September 1992 through 25 September 1992

ER -

Scan cell design for enhanced delay fault testability

Abstract

Other

Access to Document

Fingerprint

Cite this