Scan cell design for enhanced delay fault testability

Gerrit van Brakel, G. van Brakel, Yizi Xing, Y. Xing, Hans G. Kerkhoff

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    Abstract

    Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell
    Original languageUndefined
    Title of host publicationProceedings IEEE ASIC'92
    Place of PublicationRochester, NY
    PublisherIEEE
    Pages372-375
    Number of pages0
    ISBN (Print)9780780307681
    DOIs
    Publication statusPublished - 1 Sep 1992
    EventFifth Annual IEEE International ASIC Conference and Exhibit - Rochester, NY
    Duration: 21 Sep 199225 Sep 1992

    Publication series

    Name
    PublisherIEEE

    Other

    OtherFifth Annual IEEE International ASIC Conference and Exhibit
    Period21/09/9225/09/92
    OtherSeptember 21-25, 1992

    Keywords

    • METIS-112958
    • IR-16074

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