Scan Test Strategy for Asynchronous-Synchronous Interfaces

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    Abstract

    In the next few years, the well-known synchronous design style will not be able to keep pace with the increase of speed and capabilities of integration of advanced processes. Asynchronous design will become more and more common among digital designs, while synchronous-asynchronous interactions will emerge as a key issue in future SoC designs. This paper presents test strategies for 2-phase asynchronous-synchronous, and vice versa, interfaces. It is shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors are able to test all the stuck-at-faults within the asynchronous-synchronous interfaces.
    Original languageUndefined
    Title of host publicationProceedings of IEEE European Test Workshop ETW
    Place of PublicationMaastricht, The Netherlands
    PublisherIEEE
    Pages43-50
    Number of pages8
    ISBN (Print)0-7695-1908-3
    Publication statusPublished - 1 Mar 2003
    EventEighth IEEE European Test Workshop - Maastricht, The Netherlands
    Duration: 25 May 200328 May 2003

    Publication series

    Name
    PublisherIEEE
    ISSN (Print)1530-1877

    Workshop

    WorkshopEighth IEEE European Test Workshop
    Period25/05/0328/05/03
    Other25-28 May 2003

    Keywords

    • METIS-214887
    • IR-46399

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