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Scheduling and Allocation for the High-level Synthesis of DSP Algorithms by Exploitation of Data Transfer Mobility

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    Abstract

    A scheduling and allocation method is given for the high-level synthesis of DSP algorithms described by iterative data flow graphs. The method is based on the concept of scheduling ranges. It generates overlapped schedules, while performing retiming and loop folding implicitly. The scheduler operates on the input and output data transfers of the operations in the graph, allowing a trade-off of functional units against buses. For each transfer a scheduling range is computed and the optimal position within this range is found by modified force-directed scheduling. The method has obtained optimal results for well-known benchmark examples.
    Original languageEnglish
    Title of host publicationThe 1992 International Conference on Computer Systems and Software Engineering CompEuro 92
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages145-150
    Number of pages6
    ISBN (Print)0-8186-2760-3
    DOIs
    Publication statusPublished - 2 May 1992
    EventInternational Conference on Computer Systems and Software Engineering, CompEuro 1992 - The Hague, Netherlands
    Duration: 4 May 19928 May 1992

    Conference

    ConferenceInternational Conference on Computer Systems and Software Engineering, CompEuro 1992
    Abbreviated titleCompEuro 1992
    Country/TerritoryNetherlands
    CityThe Hague
    Period4/05/928/05/92

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