Selection of tests for outlier detection

H.C.M. Bossers; Johann L. Hurink; Gerardus Johannes Maria Smit

doi:10.1109/VTS.2013.6548885

Selection of tests for outlier detection

H.C.M. Bossers, Johann L. Hurink, Gerardus Johannes Maria Smit

Discrete Mathematics and Mathematical Programming

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

5 Downloads (Pure)

Abstract

Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.

Original language	Undefined
Title of host publication	31st IEEE VLSI Test Symposium, VTS 2013
Place of Publication	USA
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Print)	978-1-4673-5542-1
DOIs	https://doi.org/10.1109/VTS.2013.6548885
Publication status	Published - Apr 2013
Event	31st IEEE VLSI Test Symposium, VTS 2013 - Berkeley, United States Duration: 29 Apr 2013 → 2 May 2013 Conference number: 31

Publication series

Name
Publisher	IEEE Computer Society
ISSN (Print)	1093-0167

Conference

Conference	31st IEEE VLSI Test Symposium, VTS 2013
Abbreviated title	VTS
Country/Territory	United States
City	Berkeley
Period	29/04/13 → 2/05/13

Keywords

EWI-22670
Integrated circuits
Reliability
METIS-297594
Test selection
IR-86906
Adaptive test
Outlier Detection

Access to Document

10.1109/VTS.2013.6548885

http://eprints.eemcs.utwente.nl/secure2/22670/01/fulltext_bossers_VTS2013.pdf

Cite this

@inproceedings{85689bc81a6144b29461088909fbaf03,

title = "Selection of tests for outlier detection",

abstract = "Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.",

keywords = "EWI-22670, Integrated circuits, Reliability, METIS-297594, Test selection, IR-86906, Adaptive test, Outlier Detection",

author = "H.C.M. Bossers and Hurink, {Johann L.} and Smit, {Gerardus Johannes Maria}",

note = "10.1109/VTS.2013.6548885 ; 31st IEEE VLSI Test Symposium, VTS 2013 ; Conference date: 29-04-2013 Through 02-05-2013",

year = "2013",

month = apr,

doi = "10.1109/VTS.2013.6548885",

language = "Undefined",

isbn = "978-1-4673-5542-1",

publisher = "IEEE",

pages = "1--6",

booktitle = "31st IEEE VLSI Test Symposium, VTS 2013",

address = "United States",

}

TY - GEN

T1 - Selection of tests for outlier detection

AU - Bossers, H.C.M.

AU - Hurink, Johann L.

AU - Smit, Gerardus Johannes Maria

N1 - Conference code: 31

PY - 2013/4

Y1 - 2013/4

N2 - Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.

AB - Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.

KW - EWI-22670

KW - Integrated circuits

KW - Reliability

KW - METIS-297594

KW - Test selection

KW - IR-86906

KW - Adaptive test

KW - Outlier Detection

U2 - 10.1109/VTS.2013.6548885

DO - 10.1109/VTS.2013.6548885

M3 - Conference contribution

SN - 978-1-4673-5542-1

SP - 1

EP - 6

BT - 31st IEEE VLSI Test Symposium, VTS 2013

PB - IEEE

CY - USA

T2 - 31st IEEE VLSI Test Symposium, VTS 2013

Y2 - 29 April 2013 through 2 May 2013

ER -