Selection of tests for outlier detection

H.C.M. Bossers, Johann L. Hurink, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)


Integrated circuits are tested thoroughly in order to meet the high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited. In this paper we introduce a mathematical framework, that given a set of target devices, can select tests for outlier detection and set the parameters for each outlier detection method. We provide results on real world data and analyze the resulting yield loss and missed targets.
Original languageUndefined
Title of host publication31st IEEE VLSI Test Symposium, VTS 2013
Place of PublicationUSA
PublisherIEEE Computer Society
Number of pages6
ISBN (Print)978-1-4673-5542-1
Publication statusPublished - Apr 2013
Event31st IEEE VLSI Test Symposium, VTS 2013 - Berkeley, United States
Duration: 29 Apr 20132 May 2013
Conference number: 31

Publication series

PublisherIEEE Computer Society
ISSN (Print)1093-0167


Conference31st IEEE VLSI Test Symposium, VTS 2013
Abbreviated titleVTS
Country/TerritoryUnited States


  • EWI-22670
  • Integrated circuits
  • Reliability
  • METIS-297594
  • Test selection
  • IR-86906
  • Adaptive test
  • Outlier Detection

Cite this