Abstract
A solid-phase epitaxy (SPE) process based on material inversion of an amorphous silicon (α-Si) on aluminum layer-stack is applied to form ultrashallow p-type junctions. In this paper, we demonstrate the controllability of the whole process when the junction area is reduced to the sub-100-nm range and the processing temperature is reduced to 400°C. The SPE-Si to Si-substrate interface, analyzed locally by transmission electron microscopy and more systematically by the fabrication and electrical characterization of p+ -n diodes, was found to be practically defect-free. Moreover, it is demonstrated by capacitance-voltage profiling that the Al-dopants do not diffuse into the bulk silicon for the used processing temperatures and the SPE p+ -island to n-substrate transition is ideally abrupt. The I-V characteristics of the as-fabricated p+-n diodes are near ideal (n = 1.03) and low-ohmic contact resistance to p- and p+ regions is reliably obtained.
Original language | English |
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Pages (from-to) | 196-200 |
Number of pages | 5 |
Journal | IEEE transactions on nanotechnology |
Volume | 6 |
Issue number | 2 |
DOIs | |
Publication status | Published - 1 Mar 2007 |
Externally published | Yes |
Keywords
- Al-doping
- Elevated source/drain
- Low-ohmic contacts
- Low-temperature processing
- Metal-induced crystallization
- p-n-p bipolar junction transistors
- Selective epitaxial growth
- Solid-phase epitaxy
- Ultrashallow junctions