Abstract
This paper proposes a general definition of self-stabilizing wait-free shared memory objects. The definition ensures that, even in the face of processor failures, every execution after a transient memory failure is linearizable except for an a priori bounded number of actions. Shared registers have been used extensively as communication medium in self-stabilizing protocols. As an application of our theory, we therefore focus on self-stabilizing implementation of such registers, thus providing a large body of previous research with a more solid foundation. In particular, we prove that one cannot construct a self-stabilizing single-reader single-writer regular bit from self-stabilizing single-reader single-writer safe bits, using only a single bit for the writer. This leads us to postulate a self-stabilizing dual-reader single-writer safe bit as the minimal hardware needed to achieve self-stabilizing wait-free interprocess communication and synchronization. Based on this hardware, adaptations of well-known wait-free implementations of regular and atomic shared registers are proven to be self-stabilizing.
Original language | Undefined |
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Pages (from-to) | 766-791 |
Journal | Journal of parallel and distributed computing |
Volume | 62 |
Issue number | 5 |
DOIs | |
Publication status | Published - 2002 |
Keywords
- IR-74779
- wait-free constructions
- Distributed Computing
- METIS-211555
- Shared memory
- Fault Tolerance
- self-stabilization