Signal sampling circuit

S.M. Louwsma (Inventor), Maarten Vertregt (Inventor)

    Research output: Patent

    15 Downloads (Pure)

    Abstract

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. The holding time period comprises a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.
    Original languageUndefined
    Patent numberUS2010207792(A1)
    Priority date13/09/07
    Publication statusPublished - 19 Aug 2010

    Keywords

    • EWI-15332
    • IR-73467
    • METIS-270687

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