Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress

M.S.B. Sowariraj, Peter C. de Jong, Cora Salm, Theo Smedes, A.J. Mouthaan, F.G. Kuper

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Citations (Scopus)
    9 Downloads (Pure)

    Abstract

    In CDM type of ESD, the IC is both the source and part of discharge current path. To study the CDM performance of an ICI a ull-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are the various package capacitors. The CDM circuit models presented before only nclude the capacitors formed by the IC circuit design on the package and not that of die attachment plate on which the die is placed. This paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.
    Original languageEnglish
    Title of host publication2005 IEEE International Reliability Physics Symposium proceedings
    Subtitle of host publication43rd annual : San Jose, California, April 17-21, 2005
    Place of PublicationPiscataway, NJ
    PublisherIEEE Computer Society
    Pages608-609
    Number of pages2
    ISBN (Print)9780780388031
    DOIs
    Publication statusPublished - Apr 2005
    Event43th Annual IEEE International Reliability Physics Symposium, IRPS 2005 - San Jose, United States
    Duration: 17 Apr 200521 Apr 2005
    Conference number: 43

    Conference

    Conference43th Annual IEEE International Reliability Physics Symposium, IRPS 2005
    Abbreviated titleIRPS
    CountryUnited States
    CitySan Jose
    Period17/04/0521/04/05

    Keywords

    • CDM
    • IR-51074
    • EWI-15517
    • METIS-224037

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  • Cite this

    Sowariraj, M. S. B., de Jong, P. C., Salm, C., Smedes, T., Mouthaan, A. J., & Kuper, F. G. (2005). Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress. In 2005 IEEE International Reliability Physics Symposium proceedings: 43rd annual : San Jose, California, April 17-21, 2005 (pp. 608-609). Piscataway, NJ: IEEE Computer Society. https://doi.org/10.1109/RELPHY.2005.1493166