Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress

M.S.B. Sowariraj; Peter C. de Jong; Cora Salm; Theo Smedes; A.J. Mouthaan; F.G. Kuper

doi:10.1109/RELPHY.2005.1493166

Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress

M.S.B. Sowariraj, Peter C. de Jong, Cora Salm, Theo Smedes, A.J. Mouthaan, F.G. Kuper

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

15 Downloads (Pure)

Abstract

In CDM type of ESD, the IC is both the source and part of discharge current path. To study the CDM performance of an ICI a ull-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are the various package capacitors. The CDM circuit models presented before only nclude the capacitors formed by the IC circuit design on the package and not that of die attachment plate on which the die is placed. This paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.

Original language	English
Title of host publication	2005 IEEE International Reliability Physics Symposium proceedings
Subtitle of host publication	43rd annual : San Jose, California, April 17-21, 2005
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	608-609
Number of pages	2
ISBN (Print)	9780780388031
DOIs	https://doi.org/10.1109/RELPHY.2005.1493166
Publication status	Published - Apr 2005
Event	43th Annual IEEE International Reliability Physics Symposium, IRPS 2005 - San Jose, United States Duration: 17 Apr 2005 → 21 Apr 2005 Conference number: 43

Conference

Conference	43th Annual IEEE International Reliability Physics Symposium, IRPS 2005
Abbreviated title	IRPS
Country/Territory	United States
City	San Jose
Period	17/04/05 → 21/04/05

Keywords

CDM
IR-51074
EWI-15517
METIS-224037

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10.1109/RELPHY.2005.1493166

Cite this

Sowariraj, M. S. B., de Jong, P. C., Salm, C., Smedes, T., Mouthaan, A. J., & Kuper, F. G. (2005). Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress. In 2005 IEEE International Reliability Physics Symposium proceedings: 43rd annual : San Jose, California, April 17-21, 2005 (pp. 608-609). IEEE. https://doi.org/10.1109/RELPHY.2005.1493166

@inproceedings{dd8df2cdd7ab484aa6aa470ab3ac4605,

title = "Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress",

abstract = "In CDM type of ESD, the IC is both the source and part of discharge current path. To study the CDM performance of an ICI a ull-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are the various package capacitors. The CDM circuit models presented before only nclude the capacitors formed by the IC circuit design on the package and not that of die attachment plate on which the die is placed. This paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.",

keywords = "CDM, IR-51074, EWI-15517, METIS-224037",

author = "M.S.B. Sowariraj and \{de Jong\}, \{Peter C.\} and Cora Salm and Theo Smedes and A.J. Mouthaan and F.G. Kuper",

note = "INSPEC Accession Number:8463619; 43th Annual IEEE International Reliability Physics Symposium, IRPS 2005, IRPS ; Conference date: 17-04-2005 Through 21-04-2005",

year = "2005",

month = apr,

doi = "10.1109/RELPHY.2005.1493166",

language = "English",

isbn = "9780780388031",

pages = "608--609",

booktitle = "2005 IEEE International Reliability Physics Symposium proceedings",

publisher = "IEEE",

address = "United States",

}

Sowariraj, MSB, de Jong, PC, Salm, C, Smedes, T, Mouthaan, AJ & Kuper, FG 2005, Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress. in 2005 IEEE International Reliability Physics Symposium proceedings: 43rd annual : San Jose, California, April 17-21, 2005. IEEE, Piscataway, NJ, pp. 608-609, 43th Annual IEEE International Reliability Physics Symposium, IRPS 2005, San Jose, California, United States, 17/04/05. https://doi.org/10.1109/RELPHY.2005.1493166

Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress. / Sowariraj, M.S.B.; de Jong, Peter C.; Salm, Cora et al.
2005 IEEE International Reliability Physics Symposium proceedings: 43rd annual : San Jose, California, April 17-21, 2005. Piscataway, NJ: IEEE, 2005. p. 608-609.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress

AU - Sowariraj, M.S.B.

AU - de Jong, Peter C.

AU - Salm, Cora

AU - Smedes, Theo

AU - Mouthaan, A.J.

AU - Kuper, F.G.

N1 - Conference code: 43

PY - 2005/4

Y1 - 2005/4

N2 - In CDM type of ESD, the IC is both the source and part of discharge current path. To study the CDM performance of an ICI a ull-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are the various package capacitors. The CDM circuit models presented before only nclude the capacitors formed by the IC circuit design on the package and not that of die attachment plate on which the die is placed. This paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.

AB - In CDM type of ESD, the IC is both the source and part of discharge current path. To study the CDM performance of an ICI a ull-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are the various package capacitors. The CDM circuit models presented before only nclude the capacitors formed by the IC circuit design on the package and not that of die attachment plate on which the die is placed. This paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.

KW - CDM

KW - IR-51074

KW - EWI-15517

KW - METIS-224037

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DO - 10.1109/RELPHY.2005.1493166

M3 - Conference contribution

SN - 9780780388031

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EP - 609

BT - 2005 IEEE International Reliability Physics Symposium proceedings

PB - IEEE

CY - Piscataway, NJ

T2 - 43th Annual IEEE International Reliability Physics Symposium, IRPS 2005

Y2 - 17 April 2005 through 21 April 2005

ER -

Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress

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Keywords

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