Silicon Nanowire Fabrication Using Edge and Corner Lithography

H. Yagubizade; Johan W. Berenschot; Henricus V. Jansen; Michael Curt Elwenspoek; Niels Roelof Tas

doi:10.1109/NMDC.2010.5652181

Silicon Nanowire Fabrication Using Edge and Corner Lithography

H. Yagubizade, Johan W. Berenschot, Henricus V. Jansen, Michael Curt Elwenspoek, Niels Roelof Tas

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

197 Downloads (Pure)

Abstract

This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features to the formed. The pattern formed by conventional microlithography determines the location. The presented method is based on the low etch rate of <111>-planes. Initially, using edge lithography, nanoridges with ∼71° angle with the wafer surface and bound by <111>-planes are fabricated. Thereafter, corner lithography is used. The fabricated SiNWs can be isolated from the substrate by oxidation of the thin silicon base.

Original language	Undefined
Title of host publication	IEEE Nanotechnology Materials and Devices Conference, NMDC 2010
Place of Publication	Monterey
Publisher	IEEE
Pages	128-131
Number of pages	4
ISBN (Print)	978-1-4244-8896-4
DOIs	https://doi.org/10.1109/NMDC.2010.5652181
Publication status	Published - 12 Oct 2010
Event	IEEE Nanotechnology Materials and Devices Conference, NMDC 2010, Monterey, CA, USA: IEEE Nanotechnology Materials and Devices Conference, NMDC 2010 - Monterey Duration: 12 Oct 2010 → …

Publication series

Name
Publisher	IEEE

Conference

Conference	IEEE Nanotechnology Materials and Devices Conference, NMDC 2010, Monterey, CA, USA
City	Monterey
Period	12/10/10 → …

Keywords

IR-75032
EWI-18565
METIS-275667

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/NMDC.2010.5652181

Cite this

@inproceedings{858462a91a0049edb6784986a2515544,

title = "Silicon Nanowire Fabrication Using Edge and Corner Lithography",

abstract = "This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features to the formed. The pattern formed by conventional microlithography determines the location. The presented method is based on the low etch rate of <111>-planes. Initially, using edge lithography, nanoridges with ∼71° angle with the wafer surface and bound by <111>-planes are fabricated. Thereafter, corner lithography is used. The fabricated SiNWs can be isolated from the substrate by oxidation of the thin silicon base.",

keywords = "IR-75032, EWI-18565, METIS-275667",

author = "H. Yagubizade and Berenschot, {Johan W.} and Jansen, {Henricus V.} and Elwenspoek, {Michael Curt} and Tas, {Niels Roelof}",

note = "10.1109/NMDC.2010.5652181 ; IEEE Nanotechnology Materials and Devices Conference, NMDC 2010, Monterey, CA, USA ; Conference date: 12-10-2010",

year = "2010",

month = oct,

day = "12",

doi = "10.1109/NMDC.2010.5652181",

language = "Undefined",

isbn = "978-1-4244-8896-4",

publisher = "IEEE",

pages = "128--131",

booktitle = "IEEE Nanotechnology Materials and Devices Conference, NMDC 2010",

address = "United States",

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Yagubizade, H, Berenschot, JW, Jansen, HV, Elwenspoek, MC & Tas, NR 2010, Silicon Nanowire Fabrication Using Edge and Corner Lithography. in IEEE Nanotechnology Materials and Devices Conference, NMDC 2010. IEEE, Monterey, pp. 128-131, IEEE Nanotechnology Materials and Devices Conference, NMDC 2010, Monterey, CA, USA, Monterey, 12/10/10. https://doi.org/10.1109/NMDC.2010.5652181

TY - GEN

T1 - Silicon Nanowire Fabrication Using Edge and Corner Lithography

AU - Yagubizade, H.

AU - Berenschot, Johan W.

AU - Jansen, Henricus V.

AU - Elwenspoek, Michael Curt

AU - Tas, Niels Roelof

N1 - 10.1109/NMDC.2010.5652181

PY - 2010/10/12

Y1 - 2010/10/12

N2 - This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features to the formed. The pattern formed by conventional microlithography determines the location. The presented method is based on the low etch rate of <111>-planes. Initially, using edge lithography, nanoridges with ∼71° angle with the wafer surface and bound by <111>-planes are fabricated. Thereafter, corner lithography is used. The fabricated SiNWs can be isolated from the substrate by oxidation of the thin silicon base.

AB - This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features to the formed. The pattern formed by conventional microlithography determines the location. The presented method is based on the low etch rate of <111>-planes. Initially, using edge lithography, nanoridges with ∼71° angle with the wafer surface and bound by <111>-planes are fabricated. Thereafter, corner lithography is used. The fabricated SiNWs can be isolated from the substrate by oxidation of the thin silicon base.

KW - IR-75032

KW - EWI-18565

KW - METIS-275667

U2 - 10.1109/NMDC.2010.5652181

DO - 10.1109/NMDC.2010.5652181

M3 - Conference contribution

SN - 978-1-4244-8896-4

SP - 128

EP - 131

BT - IEEE Nanotechnology Materials and Devices Conference, NMDC 2010

PB - IEEE

CY - Monterey

T2 - IEEE Nanotechnology Materials and Devices Conference, NMDC 2010, Monterey, CA, USA

Y2 - 12 October 2010

ER -