Simulating NBTI degradation in arbitrary stressed analog/mixed-signal environments

Jinbo Wan; Hans G. Kerkhoff; Jaap Bisschop

doi:10.1109/TNANO.2015.2505092

Simulating NBTI degradation in arbitrary stressed analog/mixed-signal environments

Jinbo Wan
, Hans G. Kerkhoff
, Jaap Bisschop

Research output: Contribution to journal › Article › Academic › peer-review

13 Citations (Scopus)

21 Downloads (Pure)

Abstract

A compact negative bias temperature instability (NBTI) model is presented by iteratively solving the RD equations in a simple way. The new compact model can handle arbitrary stress conditions without solving time-consuming equations, and is hence, suitable for analogue/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of ageing into account. The simulation speed has increased at least a thousand times compared to classical RD models. The performance of the model has been validated by both RD theoretical solutions and 140-nm CMOS silicon measurement.

Original language	English
Pages (from-to)	137-148
Number of pages	12
Journal	IEEE transactions on nanotechnology
Volume	15
Issue number	2
DOIs	https://doi.org/10.1109/TNANO.2015.2505092
Publication status	Published - Mar 2016
Event	Final Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, MEDIAN 2015 - Tallinn, Estonia Duration: 10 Nov 2015 → 11 Nov 2015

Keywords

Analog
Reaction-diffusion
Reliability
CMOS
NBTI
n/a OA procedure

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10.1109/TNANO.2015.2505092

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title = "Simulating NBTI degradation in arbitrary stressed analog/mixed-signal environments",

abstract = "A compact negative bias temperature instability (NBTI) model is presented by iteratively solving the RD equations in a simple way. The new compact model can handle arbitrary stress conditions without solving time-consuming equations, and is hence, suitable for analogue/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of ageing into account. The simulation speed has increased at least a thousand times compared to classical RD models. The performance of the model has been validated by both RD theoretical solutions and 140-nm CMOS silicon measurement.",

keywords = "Analog, Reaction-diffusion, Reliability, CMOS, NBTI, n/a OA procedure",

author = "Jinbo Wan and Kerkhoff, \{Hans G.\} and Jaap Bisschop",

year = "2016",

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doi = "10.1109/TNANO.2015.2505092",

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T1 - Simulating NBTI degradation in arbitrary stressed analog/mixed-signal environments

AU - Wan, Jinbo

AU - Kerkhoff, Hans G.

AU - Bisschop, Jaap

PY - 2016/3

Y1 - 2016/3

N2 - A compact negative bias temperature instability (NBTI) model is presented by iteratively solving the RD equations in a simple way. The new compact model can handle arbitrary stress conditions without solving time-consuming equations, and is hence, suitable for analogue/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of ageing into account. The simulation speed has increased at least a thousand times compared to classical RD models. The performance of the model has been validated by both RD theoretical solutions and 140-nm CMOS silicon measurement.

AB - A compact negative bias temperature instability (NBTI) model is presented by iteratively solving the RD equations in a simple way. The new compact model can handle arbitrary stress conditions without solving time-consuming equations, and is hence, suitable for analogue/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of ageing into account. The simulation speed has increased at least a thousand times compared to classical RD models. The performance of the model has been validated by both RD theoretical solutions and 140-nm CMOS silicon measurement.

KW - Analog

KW - Reaction-diffusion

KW - Reliability

KW - CMOS

KW - NBTI

KW - n/a OA procedure

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DO - 10.1109/TNANO.2015.2505092

M3 - Article

SN - 1536-125X

VL - 15

SP - 137

EP - 148

JO - IEEE transactions on nanotechnology

JF - IEEE transactions on nanotechnology

IS - 2

T2 - Final Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, MEDIAN 2015

Y2 - 10 November 2015 through 11 November 2015

ER -

Simulating NBTI degradation in arbitrary stressed analog/mixed-signal environments

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Keywords

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