As schrinking of feature size in integrated circuits and increasing of packing density continue, it becomes incrementally important to take into account the interconnect layout features which can limit the risk of electromigration failure and improve the reliability of intervonnect systems. However, hardly any information is available on the reservoir and via layout effects on electromigration. In this paper, we characterized the influence of via count and current crowding effects on electromigration lifetime in different via and reservoir layouts design through simulation and experiments. We observe a negligible difference in electromigration lifteime for structures having the same reservoir area, irrespective of the contact/via configuration. The effect of current crowding on electromigration lifetime after an increasing of the current density stress was still small. The highest tensile stress point obtained from simulations coincides with the experimentally found void locations.