Slack Exploitation for Aggressive Dynamic Power Reduction in SoC

A. Milutinovic, Kees Goossens, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

The increasing power consumption of today’s system-on-chip (SoC) outpaces the trend of increasing battery capacity. The applications offered to customers grow tremendously too, a trend that is accelerating in the future. This yields stronger requirements for lower power consumption. During design, a system is dimensioned to worst-case workload requirements. Most of the time, workload is far below this level, which results in slack in some parts of the system. Our idea is to exploit this available slack by using adequate variants of dynamic voltage and frequency scaling and power gating. For scalability reasons, we commence our research with local dynamic adaptive power and frequency scaling, based on the slack observed at run time. This paper presents the motivations and possible directions for our research.
Original languageUndefined
Title of host publicationProceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007
Place of PublicationUtrecht
PublisherSTW
Pages-
Number of pages6
ISBN (Print)978-90-73461-49-9
Publication statusPublished - 2007
Event18th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2007 - Veldhoven, Netherlands
Duration: 29 Nov 200730 Nov 2007
Conference number: 18

Publication series

Name
PublisherTechnology Foundation / SAFE &ProRISC
Number412

Conference

Conference18th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2007
CountryNetherlands
CityVeldhoven
Period29/11/0730/11/07

Keywords

  • EWI-15040
  • dynamic power reduction
  • System on Chip
  • METIS-255487
  • slack exploitation
  • IR-65376
  • tiled architecture

Cite this

Milutinovic, A., Goossens, K., & Smit, G. J. M. (2007). Slack Exploitation for Aggressive Dynamic Power Reduction in SoC. In Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007 (pp. -). Utrecht: STW.
Milutinovic, A. ; Goossens, Kees ; Smit, Gerardus Johannes Maria. / Slack Exploitation for Aggressive Dynamic Power Reduction in SoC. Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007. Utrecht : STW, 2007. pp. -
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title = "Slack Exploitation for Aggressive Dynamic Power Reduction in SoC",
abstract = "The increasing power consumption of today’s system-on-chip (SoC) outpaces the trend of increasing battery capacity. The applications offered to customers grow tremendously too, a trend that is accelerating in the future. This yields stronger requirements for lower power consumption. During design, a system is dimensioned to worst-case workload requirements. Most of the time, workload is far below this level, which results in slack in some parts of the system. Our idea is to exploit this available slack by using adequate variants of dynamic voltage and frequency scaling and power gating. For scalability reasons, we commence our research with local dynamic adaptive power and frequency scaling, based on the slack observed at run time. This paper presents the motivations and possible directions for our research.",
keywords = "EWI-15040, dynamic power reduction, System on Chip, METIS-255487, slack exploitation, IR-65376, tiled architecture",
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Milutinovic, A, Goossens, K & Smit, GJM 2007, Slack Exploitation for Aggressive Dynamic Power Reduction in SoC. in Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007. STW, Utrecht, pp. -, 18th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2007, Veldhoven, Netherlands, 29/11/07.

Slack Exploitation for Aggressive Dynamic Power Reduction in SoC. / Milutinovic, A.; Goossens, Kees; Smit, Gerardus Johannes Maria.

Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007. Utrecht : STW, 2007. p. -.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AU - Goossens, Kees

AU - Smit, Gerardus Johannes Maria

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Y1 - 2007

N2 - The increasing power consumption of today’s system-on-chip (SoC) outpaces the trend of increasing battery capacity. The applications offered to customers grow tremendously too, a trend that is accelerating in the future. This yields stronger requirements for lower power consumption. During design, a system is dimensioned to worst-case workload requirements. Most of the time, workload is far below this level, which results in slack in some parts of the system. Our idea is to exploit this available slack by using adequate variants of dynamic voltage and frequency scaling and power gating. For scalability reasons, we commence our research with local dynamic adaptive power and frequency scaling, based on the slack observed at run time. This paper presents the motivations and possible directions for our research.

AB - The increasing power consumption of today’s system-on-chip (SoC) outpaces the trend of increasing battery capacity. The applications offered to customers grow tremendously too, a trend that is accelerating in the future. This yields stronger requirements for lower power consumption. During design, a system is dimensioned to worst-case workload requirements. Most of the time, workload is far below this level, which results in slack in some parts of the system. Our idea is to exploit this available slack by using adequate variants of dynamic voltage and frequency scaling and power gating. For scalability reasons, we commence our research with local dynamic adaptive power and frequency scaling, based on the slack observed at run time. This paper presents the motivations and possible directions for our research.

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Milutinovic A, Goossens K, Smit GJM. Slack Exploitation for Aggressive Dynamic Power Reduction in SoC. In Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007. Utrecht: STW. 2007. p. -