Slack Exploitation for Aggressive Dynamic Power Reduction in SoC

A. Milutinovic, Kees Goossens, Gerardus Johannes Maria Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    31 Downloads (Pure)


    The increasing power consumption of today’s system-on-chip (SoC) outpaces the trend of increasing battery capacity. The applications offered to customers grow tremendously too, a trend that is accelerating in the future. This yields stronger requirements for lower power consumption. During design, a system is dimensioned to worst-case workload requirements. Most of the time, workload is far below this level, which results in slack in some parts of the system. Our idea is to exploit this available slack by using adequate variants of dynamic voltage and frequency scaling and power gating. For scalability reasons, we commence our research with local dynamic adaptive power and frequency scaling, based on the slack observed at run time. This paper presents the motivations and possible directions for our research.
    Original languageUndefined
    Title of host publicationProceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007
    Place of PublicationUtrecht
    Number of pages6
    ISBN (Print)978-90-73461-49-9
    Publication statusPublished - 2007
    Event18th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2007 - Veldhoven, Netherlands
    Duration: 29 Nov 200730 Nov 2007
    Conference number: 18

    Publication series

    PublisherTechnology Foundation / SAFE &ProRISC


    Conference18th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2007


    • EWI-15040
    • dynamic power reduction
    • System on Chip
    • METIS-255487
    • slack exploitation
    • IR-65376
    • tiled architecture

    Cite this