The increasing power consumption of today’s system-on-chip (SoC) outpaces the trend of increasing battery capacity. The applications offered to customers grow tremendously too, a trend that is accelerating in the future. This yields stronger requirements for lower power consumption. During design, a system is dimensioned to worst-case workload requirements. Most of the time, workload is far below this level, which results in slack in some parts of the system. Our idea is to exploit this available slack by using adequate variants of dynamic voltage and frequency scaling and power gating. For scalability reasons, we commence our research with local dynamic adaptive power and frequency scaling, based on the slack observed at run time. This paper presents the motivations and possible directions for our research.
|Title of host publication||Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007|
|Place of Publication||Utrecht|
|Number of pages||6|
|Publication status||Published - 2007|
|Event||18th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2007 - Veldhoven, Netherlands|
Duration: 29 Nov 2007 → 30 Nov 2007
Conference number: 18
|Publisher||Technology Foundation / SAFE &ProRISC|
|Conference||18th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2007|
|Period||29/11/07 → 30/11/07|
- dynamic power reduction
- System on Chip
- slack exploitation
- tiled architecture
Milutinovic, A., Goossens, K., & Smit, G. J. M. (2007). Slack Exploitation for Aggressive Dynamic Power Reduction in SoC. In Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2007 (pp. -). Utrecht: STW.