Small-Delay Fault BIST in High-Speed Chip Interfaces

O. Petre, H.G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    41 Downloads (Pure)


    During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain. This increase has also pushed the need for higher data-transfer rates between these high-speed ICs, in order to optimize the entire PCB system. As a result, the clock/data skew can span tens of clock cycles. In order to cope with this skew, synchronization strategies have been developed which rely on either analogue or digital multitap delay-lines. In order for the synchronization mechanism to function properly, all tap-delays of the delay-line should have the same values within few percentages. This paper presents a technique, based on the oscillation method, to measure tap-delays of a delay-line with an accuracy of §10ps. A chip has also been implemented in an UMC 0.18¹m CMOS technology to prove our assumption. The measurements carried out on the chip confirmed the above mentioned accuracy.
    Original languageEnglish
    Title of host publicationProceedings SAFE & ProRISC 2004
    Subtitle of host publicationNovember 25-26 2004, Veldhoven, the Netherlands
    Place of PublicationUtrecht
    Number of pages6
    Publication statusPublished - 25 Nov 2004
    Event15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 - Veldhoven, Netherlands
    Duration: 25 Nov 200426 Nov 2004
    Conference number: 15


    Conference15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004
    Abbreviated titleProRisc


    • METIS-218955


    Dive into the research topics of 'Small-Delay Fault BIST in High-Speed Chip Interfaces'. Together they form a unique fingerprint.

    Cite this