During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain. This increase has also pushed the need for higher data-transfer rates between these high-speed ICs, in order to optimize the entire PCB system. As a result, the clock/data skew can span tens of clock cycles. In order to cope with this skew, synchronization strategies have been developed which rely on either analogue or digital multitap delay-lines. In order for the synchronization mechanism to function properly, all tap-delays of the delay-line should have the same values within few percentages. This paper presents a technique, based on the oscillation method, to measure tap-delays of a delay-line with an accuracy of §10ps. A chip has also been implemented in an UMC 0.18¹m CMOS technology to prove our assumption. The measurements carried out on the chip confirmed the above mentioned accuracy.
|Title of host publication||Proceedings SAFE & ProRISC 2004|
|Subtitle of host publication||November 25-26 2004, Veldhoven, the Netherlands|
|Place of Publication||Utrecht|
|Number of pages||6|
|Publication status||Published - 25 Nov 2004|
|Event||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 - Veldhoven, Netherlands|
Duration: 25 Nov 2004 → 26 Nov 2004
Conference number: 15
|Conference||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004|
|Period||25/11/04 → 26/11/04|
Petre, O., & Kerkhoff, H. G. (2004). Small-Delay Fault BIST in High-Speed Chip Interfaces. In Proceedings SAFE & ProRISC 2004: November 25-26 2004, Veldhoven, the Netherlands (pp. 429-434). Utrecht: STW.