Software-Based Memory Analysis Environments for In-Memory Wear-Leveling

C. Hakert, K.-H. Chen, M. Yayla, G.V.D. Bruggen, S. Blomeke, J.-J. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)


Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear-leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.
Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ISBN (Electronic)978-1-7281-4123-7
Publication statusPublished - 2020
Externally publishedYes
Event25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020 - Beijing, China
Duration: 13 Jan 202016 Jan 2020
Conference number: 25


Conference25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020
Abbreviated titleASP-DAC 2020


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