TY - JOUR
T1 - Some design aspects of a two-stage rail-to-rail CMOS op amp
AU - Gierkink, Sander L.J.
AU - Holzmann, Peter J.
AU - Wiegerink, Remco J.
AU - Wassenaar, R.F.
PY - 1999/11
Y1 - 1999/11
N2 - A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.
AB - A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.
U2 - 10.1023/A:1008317623471
DO - 10.1023/A:1008317623471
M3 - Article
VL - 21
SP - 143
EP - 152
JO - Analog integrated circuits and signal processing
JF - Analog integrated circuits and signal processing
SN - 0925-1030
IS - 2
ER -