Specifying With VHDL and Synthesis of VHDL: Two Case Studies

Egbert Molenkamp

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

    Original languageUndefined
    Title of host publicationProceedings of VIUF Fall 1995 Conference
    Place of PublicationNewton, MA, USA
    Pages2.17-2.27
    Publication statusPublished - 29 Jan 1995

    Keywords

    • METIS-119360

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