Specifying With VHDL and Synthesis of VHDL: Two Case Studies

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Original languageUndefined
    Title of host publicationProceedings of VIUF Fall 1995 Conference
    Place of PublicationNewton, MA, USA
    Pages2.17-2.27
    Publication statusPublished - 29 Jan 1995

    Keywords

    • METIS-119360

    Cite this

    Molenkamp, E. (1995). Specifying With VHDL and Synthesis of VHDL: Two Case Studies. In Proceedings of VIUF Fall 1995 Conference (pp. 2.17-2.27). Newton, MA, USA.