Spur reduction technique for sampling PLLs

X. Gao (Inventor), Ahmad Bahai (Inventor), Mounhir Bohsali (Inventor), Ali Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), Gerard Socci (Inventor)

    Research output: Patent

    47 Downloads (Pure)


    Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.
    Original languageUndefined
    Patent numberUS8373481 B2
    Priority date20/12/10
    Publication statusPublished - 12 Feb 2013


    • IR-86689
    • EWI-23521
    • METIS-297735

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