Spur reduction technique for sampling PLLs

X. Gao (Inventor), A. Bahai (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), G. Socci (Inventor)

    Research output: Patent

    10 Downloads (Pure)

    Abstract

    Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.
    Original languageUndefined
    Patent numberUS20120154003 A1
    Priority date20/12/10
    Publication statusPublished - 21 Jun 2012

    Keywords

    • METIS-276781
    • EWI-20185

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