Spur reduction technique for sampling PLLs

X. Gao; A. Bahai; Eric A.M. Klumperink; Bram Nauta; M. Bohsali; A. Djabbari; G. Socci

Spur reduction technique for sampling PLLs

X. Gao (Inventor), A. Bahai (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), G. Socci (Inventor)

Research output: Patent

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Abstract

Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Original language	Undefined
Patent number	US20120154003 A1
Priority date	20/12/10
Publication status	Published - 21 Jun 2012

Keywords

METIS-276781
EWI-20185

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US2012154003A1

http://worldwide.espacenet.com/publicationDetails/biblio?DB=worldwide.espacenet.com&II=2&ND=3&adjacent=true&locale=en_EP&FT=D&date=20120621&CC=US&NR=2012154003A1&KC=A1

1 Patent

Spur reduction technique for sampling PLLs
Gao, X. (Inventor), Bahai, A. (Inventor), Bohsali, M. (Inventor), Djabbari, A. (Inventor), Klumperink, E. A. M. (Inventor), Nauta, B. (Inventor) & Socci, G. (Inventor), 12 Feb 2013, Patent No. US8373481 B2, Priority date 20 Dec 2010, Priority No. US20100973353 20101220
Research output: Patent

Open Access
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Cite this

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AU - Bahai, A.

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AU - Djabbari, A.

AU - Socci, G.

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