Spur reduction technique for sampling PLLs

X. Gao; A. Bahai; Eric A.M. Klumperink; Bram Nauta; M. Bohsali; A. Djabbari; G. Socci

Spur reduction technique for sampling PLLs

X. Gao (Inventor), A. Bahai (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), M. Bohsali (Inventor), A. Djabbari (Inventor), G. Socci (Inventor)

Research output: Patent

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Abstract

Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Original language	Undefined
Patent number	US20120154003 A1
Priority date	20/12/10
Publication status	Published - 21 Jun 2012

Keywords

METIS-276781
EWI-20185

Access to Document

US2012154003A1
open

http://worldwide.espacenet.com/publicationDetails/biblio?DB=worldwide.espacenet.com&II=2&ND=3&adjacent=true&locale=en_EP&FT=D&date=20120621&CC=US&NR=2012154003A1&KC=A1

Cite this

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title = "Spur reduction technique for sampling PLLs",

abstract = "Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.",

keywords = "METIS-276781, EWI-20185",

author = "X. Gao and A. Bahai and Klumperink, {Eric A.M.} and Bram Nauta and M. Bohsali and A. Djabbari and G. Socci",

year = "2012",

month = jun,

day = "21",

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type = "Patent",

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TY - PAT

T1 - Spur reduction technique for sampling PLLs

AU - Gao, X.

AU - Bahai, A.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Bohsali, M.

AU - Djabbari, A.

AU - Socci, G.

PY - 2012/6/21

Y1 - 2012/6/21

N2 - Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

AB - Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

KW - METIS-276781

KW - EWI-20185

M3 - Patent

M1 - US20120154003 A1

ER -