Abstract
Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.
Original language | Undefined |
---|---|
Patent number | US20120154003 A1 |
Priority date | 20/12/10 |
Publication status | Published - 21 Jun 2012 |
Keywords
- METIS-276781
- EWI-20185