Spur reduction technique for sampling PLLs

X. Gao; Ahmad Bahai; Mounhir Bohsali; Ali Djabbari; Eric A.M. Klumperink; Bram Nauta; Gerard Socci

Spur reduction technique for sampling PLLs

X. Gao (Inventor)
, Ahmad Bahai (Inventor)
, Mounhir Bohsali (Inventor)
, Ali Djabbari (Inventor)
, Eric A.M. Klumperink (Inventor)
, Bram Nauta (Inventor)
, Gerard Socci (Inventor)

Research output: Patent

166 Downloads (Pure)

Abstract

Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Original language	Undefined
Patent number	US8373481 B2
Priority date	20/12/10
Publication status	Published - 12 Feb 2013

Keywords

IR-86689
EWI-23521
METIS-297735

Access to Document

patent-18-US8373481Final published version, 53.7 KB

http://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=8373481B2&KC=B2&FT=D&ND=4&date=20130212&DB=worldwide.espacenet.com&locale=en_EP

Spur reduction technique for sampling PLLs
Gao, X. (Inventor), Bahai, A. (Inventor), Klumperink, E. A. M. (Inventor), Nauta, B. (Inventor), Bohsali, M. (Inventor), Djabbari, A. (Inventor) & Socci, G. (Inventor), 21 Jun 2012, Patent No. US20120154003 A1, Priority date 20 Dec 2010, Priority No. 12/973,353
Research output: Patent

File

Cite this

@misc{78003ff307c04ecbb7ce8dae5dfdd537,

title = "Spur reduction technique for sampling PLLs",

abstract = "Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.",

keywords = "IR-86689, EWI-23521, METIS-297735",

author = "X. Gao and Ahmad Bahai and Mounhir Bohsali and Ali Djabbari and Klumperink, \{Eric A.M.\} and Bram Nauta and Gerard Socci",

year = "2013",

month = feb,

day = "12",

language = "Undefined",

type = "Patent",

note = "US8373481 B2",

}

TY - PAT

T1 - Spur reduction technique for sampling PLLs

AU - Gao, X.

AU - Bahai, Ahmad

AU - Bohsali, Mounhir

AU - Djabbari, Ali

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Socci, Gerard

PY - 2013/2/12

Y1 - 2013/2/12

N2 - Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

AB - Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

KW - IR-86689

KW - EWI-23521

KW - METIS-297735

M3 - Patent

M1 - US8373481 B2

ER -