Spur-reduction techniques for PLLs using sub-sampling phase detection

X. Gao, Eric A.M. Klumperink, Gerard Socci, Mounhir Bohsali, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    17 Citations (Scopus)
    88 Downloads (Pure)

    Abstract

    Abstract A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.
    Original languageEnglish
    Title of host publicationSolid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International
    Place of PublicationPiscataway
    PublisherIEEE
    Pages474-475
    Number of pages2
    ISBN (Print)978-1-4244-6033-5
    DOIs
    Publication statusPublished - 7 Feb 2010
    EventIEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, United States
    Duration: 7 Feb 201011 Feb 2010

    Conference

    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2010
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period7/02/1011/02/10

    Keywords

    • IR-72398
    • EWI-17798
    • METIS-270791

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  • Cite this

    Gao, X., Klumperink, E. A. M., Socci, G., Bohsali, M., & Nauta, B. (2010). Spur-reduction techniques for PLLs using sub-sampling phase detection. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International (pp. 474-475). Piscataway: IEEE. https://doi.org/10.1109/ISSCC.2010.5433841