Spur-reduction techniques for PLLs using sub-sampling phase detection

X. Gao; Eric A.M. Klumperink; Gerard Socci; Mounhir Bohsali; Bram Nauta

doi:10.1109/ISSCC.2010.5433841

Spur-reduction techniques for PLLs using sub-sampling phase detection

X. Gao, Eric A.M. Klumperink, Gerard Socci, Mounhir Bohsali, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

21 Citations (Scopus)

294 Downloads (Pure)

Abstract

Abstract A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18Ã‚Â¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.

Original language	English
Title of host publication	Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International
Place of Publication	Piscataway
Publisher	IEEE
Pages	474-475
Number of pages	2
ISBN (Print)	978-1-4244-6033-5
DOIs	https://doi.org/10.1109/ISSCC.2010.5433841
Publication status	Published - 7 Feb 2010
Event	IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, United States Duration: 7 Feb 2010 → 11 Feb 2010

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2010
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	7/02/10 → 11/02/10

Keywords

IR-72398
EWI-17798
METIS-270791

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10.1109/ISSCC.2010.5433841

Gao,_X._IEEE_ISSCC_2010Final published version, 565 KB

Cite this

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title = "Spur-reduction techniques for PLLs using sub-sampling phase detection",

abstract = "Abstract A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18{\~A}‚{\^A}¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.",

keywords = "IR-72398, EWI-17798, METIS-270791",

author = "X. Gao and Klumperink, {Eric A.M.} and Gerard Socci and Mounhir Bohsali and Bram Nauta",

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doi = "10.1109/ISSCC.2010.5433841",

language = "English",

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booktitle = "Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International",

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note = "IEEE International Solid-State Circuits Conference, ISSCC 2010, ISSCC ; Conference date: 07-02-2010 Through 11-02-2010",

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Gao, X, Klumperink, EAM, Socci, G, Bohsali, M & Nauta, B 2010, Spur-reduction techniques for PLLs using sub-sampling phase detection. in Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International. IEEE, Piscataway, pp. 474-475, IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, California, United States, 7/02/10. https://doi.org/10.1109/ISSCC.2010.5433841

Spur-reduction techniques for PLLs using sub-sampling phase detection. / Gao, X.; Klumperink, Eric A.M.; Socci, Gerard et al.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International. Piscataway: IEEE, 2010. p. 474-475.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Spur-reduction techniques for PLLs using sub-sampling phase detection

AU - Gao, X.

AU - Klumperink, Eric A.M.

AU - Socci, Gerard

AU - Bohsali, Mounhir

AU - Nauta, Bram

PY - 2010/2/7

Y1 - 2010/2/7

N2 - Abstract A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18Ã‚Â¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.

AB - Abstract A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18Ã‚Â¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.

KW - IR-72398

KW - EWI-17798

KW - METIS-270791

U2 - 10.1109/ISSCC.2010.5433841

DO - 10.1109/ISSCC.2010.5433841

M3 - Conference contribution

SN - 978-1-4244-6033-5

SP - 474

EP - 475

BT - Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International

PB - IEEE

CY - Piscataway

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2010

Y2 - 7 February 2010 through 11 February 2010

ER -

Spur-reduction techniques for PLLs using sub-sampling phase detection

Abstract

Conference

Keywords

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