Strategies to cope with plasma charging damage in design and layout phases

Zhichun Wang, J. Ackaert, A. Scarpa, Cora Salm, F.G. Kuper, M. Vugts

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    10 Citations (Scopus)
    888 Downloads (Pure)

    Abstract

    In this paper, strategics to cope with plasma charging damage in design and layout phases are discussed. A semi-empirical model is addressed first. With this model, a designer is able to predict the plasma charging induced yield loss of the circuit, if the antenna ratio (AR) distribution of the circuit is available. Then a novel first order self-balancing interconnect layout design is proposed to reduce the plasma charging damage. Moreover, the temperature effect on the protection diode is discussed and a strategic diode protection scheme for plasma charging damage is proposed. In addition to these general methods, a set of design rules is given to protect floating metal-insulator-metal (MIM) capacitors from plasma charging damage.
    Original languageUndefined
    Title of host publicationIEEE International Conference in Integrated Circuit and Technology (ICICDT)
    Place of PublicationPiscataway
    PublisherIEEE
    Pages91-98
    Number of pages8
    ISBN (Print)0780390814
    DOIs
    Publication statusPublished - 6 Sep 2005
    EventIEEE International Conference on Integrated Circuit and Technology: Proceedings of IEEE International Conference on Integrated Circuit and Technology - Austin, TX, USA
    Duration: 9 May 200511 May 2005

    Publication series

    Name
    PublisherIEEE

    Conference

    ConferenceIEEE International Conference on Integrated Circuit and Technology
    CityAustin, TX, USA
    Period9/05/0511/05/05

    Keywords

    • Capacitors
    • integrated circuit layout
    • IR-51076
    • plasma materials processing
    • METIS-224039
    • EWI-15510
    • MIM devices

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