Abstract
Two video frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behaviour for clock frequencies up to 25 MHz
Original language | English |
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Pages (from-to) | 639-640 |
Number of pages | 2 |
Journal | Electronics letters |
Volume | 27 |
Issue number | 8 |
DOIs | |
Publication status | Published - 1991 |
Keywords
- IR-14495
- METIS-111635