Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications

J.J.F. Rijns; Hans Wallinga

doi:10.1049/el:19910401

Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications

J.J.F. Rijns
, Hans Wallinga

Research output: Contribution to journal › Article › Academic › peer-review

6 Citations (Scopus)

259 Downloads (Pure)

Abstract

Two video frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behaviour for clock frequencies up to 25 MHz

Original language	English
Pages (from-to)	639-640
Number of pages	2
Journal	Electronics letters
Volume	27
Issue number	8
DOIs	https://doi.org/10.1049/el:19910401
Publication status	Published - 1991

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@article{33ae265fc3a14d3d89b3bc90bc8c5190,

title = "Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications",

abstract = "Two video frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behaviour for clock frequencies up to 25 MHz",

author = "J.J.F. Rijns and Hans Wallinga",

year = "1991",

doi = "10.1049/el:19910401",

language = "English",

volume = "27",

pages = "639--640",

journal = "Electronics letters",

issn = "0013-5194",

publisher = "Wiley",

number = "8",

}

TY - JOUR

T1 - Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications

AU - Rijns, J.J.F.

AU - Wallinga, Hans

PY - 1991

Y1 - 1991

N2 - Two video frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behaviour for clock frequencies up to 25 MHz

AB - Two video frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behaviour for clock frequencies up to 25 MHz

U2 - 10.1049/el:19910401

DO - 10.1049/el:19910401

M3 - Article

SN - 0013-5194

VL - 27

SP - 639

EP - 640

JO - Electronics letters

JF - Electronics letters

IS - 8

ER -

Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications

Abstract

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