### Abstract

Original language | Undefined |
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Title of host publication | Proceedings of the 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools |

Place of Publication | Los Alamitos |

Publisher | IEEE Computer Society |

Pages | 287-292 |

Number of pages | 6 |

ISBN (Print) | 978-0-7695-3782-5 |

DOIs | |

State | Published - 27 Aug 2009 |

Event | 12th EUROMICRO Conference on Digital System Design, DSD 2009 - Patras, Greece |

### Publication series

Name | |
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Publisher | IEEE Computer Society Press |

### Conference

Conference | 12th EUROMICRO Conference on Digital System Design, DSD 2009 |
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Abbreviated title | DSD |

Country | Greece |

City | Patras |

Period | 27/08/09 → 29/08/09 |

Internet address |

### Fingerprint

### Keywords

- METIS-265249
- EWI-17041
- IR-69388

### Cite this

*Proceedings of the 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools*(pp. 287-292). [10.1109/DSD.2009.141] Los Alamitos: IEEE Computer Society. DOI: 10.1109/DSD.2009.141

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*Proceedings of the 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools.*, 10.1109/DSD.2009.141, IEEE Computer Society, Los Alamitos, pp. 287-292, 12th EUROMICRO Conference on Digital System Design, DSD 2009, Patras, Greece, 27-29 August. DOI: 10.1109/DSD.2009.141

**Streaming Reduction Circuit.** / Gerards, Marco Egbertus Theodorus; Kuper, Jan; Kokkeler, Andre B.J.; Molenkamp, Egbert.

Research output: Scientific - peer-review › Conference contribution

TY - CHAP

T1 - Streaming Reduction Circuit

AU - Gerards,Marco Egbertus Theodorus

AU - Kuper,Jan

AU - Kokkeler,Andre B.J.

AU - Molenkamp,Egbert

N1 - 10.1109/DSD.2009.141

PY - 2009/8/27

Y1 - 2009/8/27

N2 - Reduction circuits are used to reduce rows of ﬂoating point values to single values. Binary ﬂoating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths can be reduced by a pipelined commutative and associative binary operator in an efficient manner. The algorithm is simple to implement, has a low latency, produces results in-order, and requires only small buffers. Besides, it uses only a single pipeline for the involved operation. The complexity of the algorithm depends on the depth of the pipeline, not on the length of the input rows. In this paper we discuss an implementation of this algorithm and we prove its correctness.

AB - Reduction circuits are used to reduce rows of ﬂoating point values to single values. Binary ﬂoating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths can be reduced by a pipelined commutative and associative binary operator in an efficient manner. The algorithm is simple to implement, has a low latency, produces results in-order, and requires only small buffers. Besides, it uses only a single pipeline for the involved operation. The complexity of the algorithm depends on the depth of the pipeline, not on the length of the input rows. In this paper we discuss an implementation of this algorithm and we prove its correctness.

KW - METIS-265249

KW - EWI-17041

KW - IR-69388

U2 - 10.1109/DSD.2009.141

DO - 10.1109/DSD.2009.141

M3 - Conference contribution

SN - 978-0-7695-3782-5

SP - 287

EP - 292

BT - Proceedings of the 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools

PB - IEEE Computer Society

ER -