Streaming Reduction Circuit

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    Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths can be reduced by a pipelined commutative and associative binary operator in an efficient manner. The algorithm is simple to implement, has a low latency, produces results in-order, and requires only small buffers. Besides, it uses only a single pipeline for the involved operation. The complexity of the algorithm depends on the depth of the pipeline, not on the length of the input rows. In this paper we discuss an implementation of this algorithm and we prove its correctness.
    Original languageEnglish
    Title of host publicationProceedings of the 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    Place of PublicationLos Alamitos
    PublisherIEEE Computer Society
    Number of pages6
    ISBN (Print)978-0-7695-3782-5
    Publication statusPublished - 27 Aug 2009
    Event12th EUROMICRO Conference on Digital System Design, DSD 2009: Architectures, Methods and Tools - Conference and Cultural Centre of the University of Patras, Patras, Greece
    Duration: 27 Aug 200929 Aug 2009
    Conference number: 12

    Publication series

    PublisherIEEE Computer Society Press


    Conference12th EUROMICRO Conference on Digital System Design, DSD 2009
    Abbreviated titleDSD
    Internet address


    • METIS-265249
    • EWI-17041
    • IR-69388


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