Study of the effects of SET induced faults on submicron technologies

A. Rohani, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

the progression of shrinking technologies into processes below 100nm has increased the importance of transient faults in digital systems. Fault injection into the HDL model of the system, known as simulation-based fault injection, is being increasingly used in recent years in order to evaluate the behaviour of systems in the presence of transient faults. However, there are still several questions in conducting simulation-based fault injections. For instance, what is the importance of timing information of the netlist with regard to the accuracy of fault injection results? And how does the number of fault injection experiments relate to obtain a realistic behaviour of the processor under test. Finally, what is the dependence of fault injection results on the processor’s workload? This paper aims to answer these questions, by studying the effects of transient faults on a post placed-androuted Verilog netlist of a high performance reconfigurable processor in 90-nanometer UMC technology.
Original languageUndefined
Title of host publication41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011
Place of PublicationUSA
PublisherIEEE Computer Society
Pages41-46
Number of pages6
ISBN (Print)978-1-4577-0374-4
DOIs
Publication statusPublished - 27 Jun 2011

Publication series

Name
PublisherIEEE Computer Society

Keywords

  • METIS-277739
  • IR-77813
  • Soft Errors
  • EWI-20391
  • SET
  • Fault injection
  • fault simulations

Cite this

Rohani, A., & Kerkhoff, H. G. (2011). Study of the effects of SET induced faults on submicron technologies. In 41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011 (pp. 41-46). USA: IEEE Computer Society. https://doi.org/10.1109/DSNW.2011.5958833
Rohani, A. ; Kerkhoff, Hans G. / Study of the effects of SET induced faults on submicron technologies. 41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011. USA : IEEE Computer Society, 2011. pp. 41-46
@inproceedings{da6ae7cd261f4c909e64d5bbcb4cece4,
title = "Study of the effects of SET induced faults on submicron technologies",
abstract = "the progression of shrinking technologies into processes below 100nm has increased the importance of transient faults in digital systems. Fault injection into the HDL model of the system, known as simulation-based fault injection, is being increasingly used in recent years in order to evaluate the behaviour of systems in the presence of transient faults. However, there are still several questions in conducting simulation-based fault injections. For instance, what is the importance of timing information of the netlist with regard to the accuracy of fault injection results? And how does the number of fault injection experiments relate to obtain a realistic behaviour of the processor under test. Finally, what is the dependence of fault injection results on the processor’s workload? This paper aims to answer these questions, by studying the effects of transient faults on a post placed-androuted Verilog netlist of a high performance reconfigurable processor in 90-nanometer UMC technology.",
keywords = "METIS-277739, IR-77813, Soft Errors, EWI-20391, SET, Fault injection, fault simulations",
author = "A. Rohani and Kerkhoff, {Hans G.}",
note = "10.1109/DSNW.2011.5958833",
year = "2011",
month = "6",
day = "27",
doi = "10.1109/DSNW.2011.5958833",
language = "Undefined",
isbn = "978-1-4577-0374-4",
publisher = "IEEE Computer Society",
pages = "41--46",
booktitle = "41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011",
address = "United States",

}

Rohani, A & Kerkhoff, HG 2011, Study of the effects of SET induced faults on submicron technologies. in 41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011. IEEE Computer Society, USA, pp. 41-46. https://doi.org/10.1109/DSNW.2011.5958833

Study of the effects of SET induced faults on submicron technologies. / Rohani, A.; Kerkhoff, Hans G.

41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011. USA : IEEE Computer Society, 2011. p. 41-46.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - Study of the effects of SET induced faults on submicron technologies

AU - Rohani, A.

AU - Kerkhoff, Hans G.

N1 - 10.1109/DSNW.2011.5958833

PY - 2011/6/27

Y1 - 2011/6/27

N2 - the progression of shrinking technologies into processes below 100nm has increased the importance of transient faults in digital systems. Fault injection into the HDL model of the system, known as simulation-based fault injection, is being increasingly used in recent years in order to evaluate the behaviour of systems in the presence of transient faults. However, there are still several questions in conducting simulation-based fault injections. For instance, what is the importance of timing information of the netlist with regard to the accuracy of fault injection results? And how does the number of fault injection experiments relate to obtain a realistic behaviour of the processor under test. Finally, what is the dependence of fault injection results on the processor’s workload? This paper aims to answer these questions, by studying the effects of transient faults on a post placed-androuted Verilog netlist of a high performance reconfigurable processor in 90-nanometer UMC technology.

AB - the progression of shrinking technologies into processes below 100nm has increased the importance of transient faults in digital systems. Fault injection into the HDL model of the system, known as simulation-based fault injection, is being increasingly used in recent years in order to evaluate the behaviour of systems in the presence of transient faults. However, there are still several questions in conducting simulation-based fault injections. For instance, what is the importance of timing information of the netlist with regard to the accuracy of fault injection results? And how does the number of fault injection experiments relate to obtain a realistic behaviour of the processor under test. Finally, what is the dependence of fault injection results on the processor’s workload? This paper aims to answer these questions, by studying the effects of transient faults on a post placed-androuted Verilog netlist of a high performance reconfigurable processor in 90-nanometer UMC technology.

KW - METIS-277739

KW - IR-77813

KW - Soft Errors

KW - EWI-20391

KW - SET

KW - Fault injection

KW - fault simulations

U2 - 10.1109/DSNW.2011.5958833

DO - 10.1109/DSNW.2011.5958833

M3 - Conference contribution

SN - 978-1-4577-0374-4

SP - 41

EP - 46

BT - 41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011

PB - IEEE Computer Society

CY - USA

ER -

Rohani A, Kerkhoff HG. Study of the effects of SET induced faults on submicron technologies. In 41st IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2011. USA: IEEE Computer Society. 2011. p. 41-46 https://doi.org/10.1109/DSNW.2011.5958833