Study on the influence of package parasitics and substrate resistance on the Charged Device Model(CDM) failure levels - possible protection methodology

Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major reason for field returns in the Integrated Circuit (IC) industry especially with downscaling of device dimensions and increased usage of automated handlers. In the case of CDM stress, the IC is both the source of static charge and part of the discharge path. Hence CDM test results are greatly affected by the package properties and the distribution of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to compare the actual discharge current flowing through the die and the protection structures for two different package materials. A general protection methodology for the ICs during CDM event, applicable to all IC design types, is suggested.