Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

M.A. Khan, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)
487 Downloads (Pure)

Abstract

In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.
Original languageUndefined
Title of host publication17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014
Place of PublicationLos Alamitos, CA, USA
PublisherIEEE
Pages15-20
Number of pages6
ISBN (Print)978-1-4799-4558-0
DOIs
Publication statusPublished - 23 Apr 2014
Event17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014 - TBD, Warsaw, Poland
Duration: 23 Apr 201425 Apr 2014
Conference number: 17
http://www.ddecs.org/

Publication series

Name
PublisherIEEE

Conference

Conference17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014
Abbreviated titleDDECS
CountryPoland
CityWarsaw
Period23/04/1425/04/14
Internet address

Keywords

  • CAES-TDT: Testable Design and Test
  • charge-redistribution SAR ADC
  • degradation modelling analysis
  • dependable design
  • METIS-305973
  • Sensitivity analysis
  • IR-91631
  • DAC capacitor-array degradation
  • EWI-24962

Cite this

Khan, M. A., & Kerkhoff, H. G. (2014). Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. In 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014 (pp. 15-20). Los Alamitos, CA, USA: IEEE. https://doi.org/10.1109/DDECS.2014.6868756
Khan, M.A. ; Kerkhoff, Hans G. / Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014. Los Alamitos, CA, USA : IEEE, 2014. pp. 15-20
@inproceedings{34e4304885d941ebafddeacc498891c0,
title = "Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs",
abstract = "In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.",
keywords = "CAES-TDT: Testable Design and Test, charge-redistribution SAR ADC, degradation modelling analysis, dependable design, METIS-305973, Sensitivity analysis, IR-91631, DAC capacitor-array degradation, EWI-24962",
author = "M.A. Khan and Kerkhoff, {Hans G.}",
note = "10.1109/DDECS.2014.6868756",
year = "2014",
month = "4",
day = "23",
doi = "10.1109/DDECS.2014.6868756",
language = "Undefined",
isbn = "978-1-4799-4558-0",
publisher = "IEEE",
pages = "15--20",
booktitle = "17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014",
address = "United States",

}

Khan, MA & Kerkhoff, HG 2014, Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. in 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014. IEEE, Los Alamitos, CA, USA, pp. 15-20, 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23/04/14. https://doi.org/10.1109/DDECS.2014.6868756

Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. / Khan, M.A.; Kerkhoff, Hans G.

17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014. Los Alamitos, CA, USA : IEEE, 2014. p. 15-20.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

AU - Khan, M.A.

AU - Kerkhoff, Hans G.

N1 - 10.1109/DDECS.2014.6868756

PY - 2014/4/23

Y1 - 2014/4/23

N2 - In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

AB - In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

KW - CAES-TDT: Testable Design and Test

KW - charge-redistribution SAR ADC

KW - degradation modelling analysis

KW - dependable design

KW - METIS-305973

KW - Sensitivity analysis

KW - IR-91631

KW - DAC capacitor-array degradation

KW - EWI-24962

U2 - 10.1109/DDECS.2014.6868756

DO - 10.1109/DDECS.2014.6868756

M3 - Conference contribution

SN - 978-1-4799-4558-0

SP - 15

EP - 20

BT - 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014

PB - IEEE

CY - Los Alamitos, CA, USA

ER -

Khan MA, Kerkhoff HG. Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. In 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014. Los Alamitos, CA, USA: IEEE. 2014. p. 15-20 https://doi.org/10.1109/DDECS.2014.6868756