Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

M.A. Khan, Hans G. Kerkhoff

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    Abstract

    In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.
    Original languageUndefined
    Title of host publication17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014
    Place of PublicationLos Alamitos, CA, USA
    PublisherIEEE
    Pages15-20
    Number of pages6
    ISBN (Print)978-1-4799-4558-0
    DOIs
    Publication statusPublished - 23 Apr 2014
    Event17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014 - TBD, Warsaw, Poland
    Duration: 23 Apr 201425 Apr 2014
    Conference number: 17
    http://www.ddecs.org/

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014
    Abbreviated titleDDECS
    CountryPoland
    CityWarsaw
    Period23/04/1425/04/14
    Internet address

    Keywords

    • CAES-TDT: Testable Design and Test
    • charge-redistribution SAR ADC
    • degradation modelling analysis
    • dependable design
    • METIS-305973
    • Sensitivity analysis
    • IR-91631
    • DAC capacitor-array degradation
    • EWI-24962

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