Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

M.A. Khan; Hans G. Kerkhoff

doi:10.1109/DDECS.2014.6868756

Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

M.A. Khan, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

773 Downloads (Pure)

Abstract

In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

Original language	Undefined
Title of host publication	17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014
Place of Publication	Los Alamitos, CA, USA
Publisher	IEEE
Pages	15-20
Number of pages	6
ISBN (Print)	978-1-4799-4558-0
DOIs	https://doi.org/10.1109/DDECS.2014.6868756
Publication status	Published - 23 Apr 2014
Event	17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014 - TBD, Warsaw, Poland Duration: 23 Apr 2014 → 25 Apr 2014 Conference number: 17 http://www.ddecs.org/

Publication series

Name
Publisher	IEEE

Conference

Conference	17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014
Abbreviated title	DDECS
Country/Territory	Poland
City	Warsaw
Period	23/04/14 → 25/04/14
Internet address	http://www.ddecs.org/

Keywords

CAES-TDT: Testable Design and Test
charge-redistribution SAR ADC
degradation modelling analysis
dependable design
METIS-305973
Sensitivity analysis
IR-91631
DAC capacitor-array degradation
EWI-24962

Access to Document

10.1109/DDECS.2014.6868756

Studying_DAC_Capacitor-Array_Degradation_in_Charge-Redistribution_SAR_ADCs

Cite this

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title = "Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs",

abstract = "In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.",

keywords = "CAES-TDT: Testable Design and Test, charge-redistribution SAR ADC, degradation modelling analysis, dependable design, METIS-305973, Sensitivity analysis, IR-91631, DAC capacitor-array degradation, EWI-24962",

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doi = "10.1109/DDECS.2014.6868756",

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Khan, MA & Kerkhoff, HG 2014, Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. in 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014. IEEE, Los Alamitos, CA, USA, pp. 15-20, 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23/04/14. https://doi.org/10.1109/DDECS.2014.6868756

Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. / Khan, M.A.; Kerkhoff, Hans G.

17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014. Los Alamitos, CA, USA : IEEE, 2014. p. 15-20.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

AB - In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

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KW - DAC capacitor-array degradation

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