A method for using hard-masks to achieve sub- 100 nm patterning of silicon is described. The process flow involves anisotropic etching of the silicon with spacers forming the hard-mask. Silicon dioxide and silicon nitride are investigated as possible spacer materials. Silicon nitride is shown to have advantages due to a better etch selectivity during the removal of the sacrificial island around which the spacers are formed. It is demonstrated that nitride spacers can be used as hard-masks for the reactive-ion etching (RIE) of silicon. Vertical silicon fins, 690 nm high and processed with an aspect-ratio of 29:1 and smooth sidewalls, were achieved on <110> bulk silicon wafers when silicon wet etching with TMAH was applied. A planarized oxide trench isolation of the base of the TMAH-etched fins is demonstrated. It opens the possibility of processing FinFETs with different channel-widths.
|Number of pages||5|
|Publication status||Published - 1 Jan 2007|
|Event||MIPRO 2007 - 30th Jubilee International Convention: Microelectronics, Electronics and Electronic Technologies, Hypermedia and Grid Systems, MEET /HGS - Opatija, Croatia|
Duration: 21 May 2007 → 25 May 2007
|Conference||MIPRO 2007 - 30th Jubilee International Convention: Microelectronics, Electronics and Electronic Technologies, Hypermedia and Grid Systems, MEET /HGS|
|Abbreviated title||MIPRO 2007|
|Period||21/05/07 → 25/05/07|