Abstract
A method for using hard-masks to achieve sub- 100 nm patterning of silicon is described. The process flow involves anisotropic etching of the silicon with spacers forming the hard-mask. Silicon dioxide and silicon nitride are investigated as possible spacer materials. Silicon nitride is shown to have advantages due to a better etch selectivity during the removal of the sacrificial island around which the spacers are formed. It is demonstrated that nitride spacers can be used as hard-masks for the reactive-ion etching (RIE) of silicon. Vertical silicon fins, 690 nm high and processed with an aspect-ratio of 29:1 and smooth sidewalls, were achieved on <110> bulk silicon wafers when silicon wet etching with TMAH was applied. A planarized oxide trench isolation of the base of the TMAH-etched fins is demonstrated. It opens the possibility of processing FinFETs with different channel-widths.
Original language | English |
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Pages | 62-66 |
Number of pages | 5 |
Publication status | Published - 1 Jan 2007 |
Externally published | Yes |
Event | MIPRO 2007 - 30th Jubilee International Convention: Microelectronics, Electronics and Electronic Technologies, Hypermedia and Grid Systems, MEET /HGS - Opatija, Croatia Duration: 21 May 2007 → 25 May 2007 |
Conference
Conference | MIPRO 2007 - 30th Jubilee International Convention: Microelectronics, Electronics and Electronic Technologies, Hypermedia and Grid Systems, MEET /HGS |
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Abbreviated title | MIPRO 2007 |
Country/Territory | Croatia |
City | Opatija |
Period | 21/05/07 → 25/05/07 |