Sub-sampling PLL techniques

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    8 Citations (Scopus)
    188 Downloads (Pure)

    Abstract

    In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N2, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter power Figure-Of-Merit (FOM). A sub-sampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N2, and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures.
    Original languageEnglish
    Title of host publicationIEEE Custom Integrated Circuits Conference, CICC 2015
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages1-8
    Number of pages8
    ISBN (Electronic)978-1-4799-8682-8
    ISBN (Print)978-1-4799-8681-1
    DOIs
    Publication statusPublished - 28 Sep 2015

    Publication series

    NameProceedings EEE Custom Integrated Circuits Conference (CICC)
    PublisherIEEE
    Volume2015
    ISSN (Print)0885-8993

    Keywords

    • EWI-26274
    • METIS-314961
    • IR-98961

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  • Cite this

    Gao, X., Klumperink, E. A. M., & Nauta, B. (2015). Sub-sampling PLL techniques. In IEEE Custom Integrated Circuits Conference, CICC 2015 (pp. 1-8). (Proceedings EEE Custom Integrated Circuits Conference (CICC); Vol. 2015). Piscataway, NJ: IEEE. https://doi.org/10.1109/CICC.2015.7338420