In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N2, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter power Figure-Of-Merit (FOM). A sub-sampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N2, and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures.
|Title of host publication||IEEE Custom Integrated Circuits Conference, CICC 2015|
|Place of Publication||Piscataway, NJ|
|Number of pages||8|
|Publication status||Published - 28 Sep 2015|
|Name||Proceedings EEE Custom Integrated Circuits Conference (CICC)|