The increasing demands for high data rate necessitate the use of complex modulation schemes that require highly linear transmitters to optimize both the signal quality and the bandwidth usage. These two metrics are usually expressed in terms of error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR). The power ampliﬁers (PAs), being the last active building block in a transmitter chain, greatly aﬀect the signal quality. Also, typically, PAs are the most power hungry block that have a signiﬁcant impact on the overall eﬃciency of a transmitter. Switch-mode class-E PAs have shown great potential for power eﬃcient ampliﬁ-cation of RF signals. Under certain conditions for the transistor voltage and cur-rent waveforms, this class of PAs provide (ideally) 100% eﬃciency. Also, due to the switched-mode operation of the transistors, class-E PAs are CMOS-friendly and show only a weak dependency on process variations. However, due to incorporating two tuned tanks, the dependency on the load impedance is relatively large, resulting in e.g. load dependent output power, power eﬃciency, peak voltages and peak (and average) currents which can lead to reliability issues. Load-mismatch can be due to (unintended) changes in the antenna environment or can be due to (intended) load modulation as with e.g. outphasing systems. This thesis work aims at high performance and reliable class-E PA. The ﬁrst part of this thesis presents load pull analyses for class-E RF power ampliﬁers from a math-ematical perspective, with analyses and discussions of the eﬀects of the most common non-idealities of class-E PAs. This includes the limited loaded quality factor (Qloaded) of the series ﬁlter, switch on-resistance, limited quality factor of the DC-feed induc-tor, load mismatch dependent switch conduction loss and the limited negative voltage excursions (due to e.g. the reverse conduction of the switch transistor for negative voltage excursions). The theoretical ﬁndings are backed up by extensive circuit simu-lations and load pull measurements of a class-E power ampliﬁer implemented in 65nm CMOS technology. Due to switch-mode operation, a single class-E with constant supply only allows phase modulation or On-Oﬀ Keying (OOK) modulation. One may use load mod-ulation through outphasing to also enable amplitude modulation. The second part of this thesis presents an analysis of outphasing class-E Power Ampliﬁers (OEPAs), using load-pull analyses of single class-E PAs. This analysis led to an approach that allows to rotate and shift power contours and rotate the eﬃciency contours to im-prove the eﬃciency of OEPAs at deep power back-oﬀ, to improve the Output Power Dynamic Range (OPDR) and to reduce switch voltage stress. The theory was vali-dated using a 65nm CMOS demonstration that includes a pcb transmission-line based power combiner. OEPAs using isolating power combiners and an inverse cosine signal component separator are inherently linear but suﬀer from low eﬃciency at power back-oﬀ. For high eﬃciency both at maximum output power and at power back-oﬀ, non-isolating power combiners are required. In the third part of this thesis the linearity of OEPAs using non-isolating power combiners is studied theoretically and validated by mea-surement of an OEPA implemented in a standard 65nm CMOS technology using an oﬀ-chip transmission-line based combiner. The developed theoretical model for the linearity is then employed to deﬁne digital pre-distortion (DPD) parameters for the implemented OEPA. Using this theory-based DPD and without any AM/AM and AM/PM characterizations, the implemented OEPA provides a competitive linearity performance compared to the state of the art OEPAs. -31dB RMS EVM level and below -30dB ACLR were measured for a 13.1dBm 6.25MHz 30Mbit/s 7dB PAPR 64QAM signal with 41.8% drain eﬃciency and 33.6% power added eﬃciency. Finally, this thesis introduces a technique to self-protect/self-heal Class-E PAs against the eﬀects of load variations, with only a minor impact on output power and eﬃciency. To validate the proposed technique, load-pull measurements are conducted on a class-E PA implemented in a standard 65nm CMOS technology, employing an oﬀ-chip matching network, augmented with a fully automated self-protective/self-healing control loop. It is shown that the proposed self-protective PA can reduce its peak switch voltage from 5.4×VDD to below 3.8×VDD for all load mismatch conditions with VSWR up to 19:1 while output power and eﬃciency are not considerably aﬀected. This allows to reduce the class-E PA’s design margins signiﬁcantly and to choose a higher VDD (to have a higher output power) compared to the case that the self-protective control loop is disabled. The designed self-protective class-E PA provides 17.5dBm measured output power from a 1.2V supply under nominal load conditions (when all the losses of the matching network are included) and the switch voltage is always below the value allowed by the technology for all load mismatch conditions with VSWR up to 19:1. Overall, this thesis contributes to design of high performance and reliable switch-mode class-E PAs.
|Qualification||Doctor of Philosophy|
|Award date||28 Oct 2020|
|Place of Publication||Enschede|
|Publication status||Published - 28 Oct 2020|