'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption

Sander L.J. Gierkink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

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    Abstract

    “Switched Biasing” is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8mm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.
    Original languageEnglish
    Title of host publicationProceedings of the 10th IEEE/ProRISC Workshop on Circuits, Systems and Signal Processing
    Place of PublicationIEEE/ProRISC Workshop in Mierlo
    Pages173-176
    Number of pages4
    Publication statusPublished - 25 Nov 1999
    Event10th ProRISC/IEEE workshop on Circuits, Systems and Signal Processing, CSSP 1999 - Mierlo, The Netherlands, Mierlo, Netherlands
    Duration: 25 Nov 199926 Nov 1999
    Conference number: 10

    Conference

    Conference10th ProRISC/IEEE workshop on Circuits, Systems and Signal Processing, CSSP 1999
    Abbreviated titleCSSP
    CountryNetherlands
    CityMierlo
    Period25/11/9926/11/99
    OtherNovember 24-26, 1999

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