'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption

Sander L.J. Gierkink; Eric A.M. Klumperink; Adrianus Johannes Maria van Tuijl; Bram Nauta

'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption

Sander L.J. Gierkink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

“Switched Biasing” is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8mm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

Original language	English
Title of host publication	Proceedings of the 10th IEEE/ProRISC Workshop on Circuits, Systems and Signal Processing
Place of Publication	IEEE/ProRISC Workshop in Mierlo
Pages	173-176
Number of pages	4
Publication status	Published - 25 Nov 1999
Event	10th ProRISC/IEEE workshop on Circuits, Systems and Signal Processing, CSSP 1999 - Mierlo, The Netherlands, Mierlo, Netherlands Duration: 25 Nov 1999 → 26 Nov 1999 Conference number: 10

Conference

Conference	10th ProRISC/IEEE workshop on Circuits, Systems and Signal Processing, CSSP 1999
Abbreviated title	CSSP
Country/Territory	Netherlands
City	Mierlo
Period	25/11/99 → 26/11/99
Other	November 24-26, 1999

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@inproceedings{8374ba6d71a2458797eaa0f083865cc1,

title = "'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption",

abstract = "“Switched Biasing” is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8mm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.",

author = "Gierkink, {Sander L.J.} and Klumperink, {Eric A.M.} and {van Tuijl}, {Adrianus Johannes Maria} and Bram Nauta",

year = "1999",

month = nov,

day = "25",

language = "English",

isbn = "90-73461-18-9",

pages = "173--176",

booktitle = "Proceedings of the 10th IEEE/ProRISC Workshop on Circuits, Systems and Signal Processing",

note = "10th ProRISC/IEEE workshop on Circuits, Systems and Signal Processing, CSSP 1999, CSSP ; Conference date: 25-11-1999 Through 26-11-1999",

}

Gierkink, SLJ, Klumperink, EAM, van Tuijl, AJM & Nauta, B 1999, 'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption. in Proceedings of the 10th IEEE/ProRISC Workshop on Circuits, Systems and Signal Processing. IEEE/ProRISC Workshop in Mierlo, pp. 173-176, 10th ProRISC/IEEE workshop on Circuits, Systems and Signal Processing, CSSP 1999, Mierlo, Netherlands, 25/11/99.

'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption. / Gierkink, Sander L.J.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria et al.
Proceedings of the 10th IEEE/ProRISC Workshop on Circuits, Systems and Signal Processing. IEEE/ProRISC Workshop in Mierlo, 1999. p. 173-176.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - 'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption

AU - Gierkink, Sander L.J.

AU - Klumperink, Eric A.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

N1 - Conference code: 10

PY - 1999/11/25

Y1 - 1999/11/25

N2 - “Switched Biasing” is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8mm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

AB - “Switched Biasing” is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8mm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

M3 - Conference contribution

SN - 90-73461-18-9

SP - 173

EP - 176

BT - Proceedings of the 10th IEEE/ProRISC Workshop on Circuits, Systems and Signal Processing

CY - IEEE/ProRISC Workshop in Mierlo

T2 - 10th ProRISC/IEEE workshop on Circuits, Systems and Signal Processing, CSSP 1999

Y2 - 25 November 1999 through 26 November 1999

ER -

'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption

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