Modern embedded systems provide a variety of functionality as operational modes, each corresponding to a mutually exclusive phase of operation. This paper provides a system level design methodology tailored for such multi-mode systems. By incorporating knowledge about the temporal behavior, it is possible to share hardware by means of partial reconfiguration on sophisticated Field Programmable Gate Arrays (FPGAs), and thus, reduce costs and improve performance. The presented methodology is based on an exploration model, which specifies the temporal behavior of the system functionality as well as the architectural characteristics of nowadays reconfigurable technology.We develop a symbolic encoding of this system specification, which enables unified system synthesis by applying sophisticated optimization techniques to perform allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The presented system-level design methodology complies with the state-of-the-art synthesis tools and communication technologies for partially reconfigurable systems. We demonstrate this by experiments on test cases from the image processing domain applying state-of-the-art technology. The results give evidence of the efficiency of the methodology and show the superiority in terms of runtime and quality of the found solutions compared to existing system-level synthesis approaches.
- Design space exploration
- Field-programmable gate arrays
- Partial reconfiguration
- System level design