System-level modelling of dynamic reconfigurable designs using functional programming abstractions

B.N. Uchevler, Kjetil Svarstad, Jan Kuper, C.P.R. Baaij

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Citations (Scopus)


    With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.
    Original languageEnglish
    Title of host publication14th International Symposium on Quality Electronic Design (ISQED)
    Place of PublicationLos Alamitos, CA, USA
    Number of pages7
    ISBN (Print)978-1-4673-4951-2
    Publication statusPublished - Mar 2013
    Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, United States
    Duration: 4 Mar 20136 Mar 2013
    Conference number: 14


    Conference14th International Symposium on Quality Electronic Design, ISQED 2013
    Abbreviated titleISQED
    Country/TerritoryUnited States
    CitySanta Clara


    • run-time reconfigurable systems
    • METIS-302553
    • dynamic reconfigurable designs
    • Partial Evaluation
    • functional programming abstractions
    • Suzaku-sz410 board
    • partial evaluation implementation technique
    • synthesizable VHDL
    • system-level modelling
    • EWI-23903
    • logic design
    • digital circuit verification
    • high-level Haskell descriptions
    • high-level descriptions
    • high-level structures
    • IR-87636
    • CLaSH tool
    • Formal verification
    • Functional HDL
    • FPGA Design
    • Hardware Description Languages
    • Field programmable gate arrays
    • Higher-order functions
    • Run-Time Reconfiguration
    • Self-Reconfiguration
    • RT level
    • EC Grant Agreement nr.: FP7/248465


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