System-level modelling of dynamic reconfigurable designs using functional programming abstractions

B.N. Uchevler; Kjetil Svarstad; Jan Kuper; C.P.R. Baaij

doi:10.1109/ISQED.2013.6523639

System-level modelling of dynamic reconfigurable designs using functional programming abstractions

B.N. Uchevler, Kjetil Svarstad, Jan Kuper, C.P.R. Baaij

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.

Original language	English
Title of host publication	14th International Symposium on Quality Electronic Design (ISQED)
Place of Publication	Los Alamitos, CA, USA
Publisher	IEEE
Pages	379-385
Number of pages	7
ISBN (Print)	978-1-4673-4951-2
DOIs	https://doi.org/10.1109/ISQED.2013.6523639
Publication status	Published - Mar 2013
Event	14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, United States Duration: 4 Mar 2013 → 6 Mar 2013 Conference number: 14

Conference

Conference	14th International Symposium on Quality Electronic Design, ISQED 2013
Abbreviated title	ISQED
Country/Territory	United States
City	Santa Clara
Period	4/03/13 → 6/03/13

Keywords

run-time reconfigurable systems
METIS-302553
dynamic reconfigurable designs
Partial Evaluation
functional programming abstractions
Suzaku-sz410 board
partial evaluation implementation technique
synthesizable VHDL
system-level modelling
EWI-23903
logic design
digital circuit verification
high-level Haskell descriptions
high-level descriptions
high-level structures
IR-87636
CLaSH tool
Formal verification
Functional HDL
FPGA Design
Hardware Description Languages
Field programmable gate arrays
Higher-order functions
Run-Time Reconfiguration
Self-Reconfiguration
RT level
EC Grant Agreement nr.: FP7/248465

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10.1109/ISQED.2013.6523639

Cite this

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title = "System-level modelling of dynamic reconfigurable designs using functional programming abstractions",

abstract = "With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.",

keywords = "run-time reconfigurable systems, METIS-302553, dynamic reconfigurable designs, Partial Evaluation, functional programming abstractions, Suzaku-sz410 board, partial evaluation implementation technique, synthesizable VHDL, system-level modelling, EWI-23903, logic design, digital circuit verification, high-level Haskell descriptions, high-level descriptions, high-level structures, IR-87636, CLaSH tool, Formal verification, Functional HDL, FPGA Design, Hardware Description Languages, Field programmable gate arrays, Higher-order functions, Run-Time Reconfiguration, Self-Reconfiguration, RT level, EC Grant Agreement nr.: FP7/248465",

author = "B.N. Uchevler and Kjetil Svarstad and Jan Kuper and C.P.R. Baaij",

note = "eemcs-eprint-23903 ; 14th International Symposium on Quality Electronic Design, ISQED 2013, ISQED ; Conference date: 04-03-2013 Through 06-03-2013",

year = "2013",

month = mar,

doi = "10.1109/ISQED.2013.6523639",

language = "English",

isbn = "978-1-4673-4951-2",

pages = "379--385",

booktitle = "14th International Symposium on Quality Electronic Design (ISQED)",

publisher = "IEEE",

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Uchevler, BN, Svarstad, K, Kuper, J & Baaij, CPR 2013, System-level modelling of dynamic reconfigurable designs using functional programming abstractions. in 14th International Symposium on Quality Electronic Design (ISQED). IEEE, Los Alamitos, CA, USA, pp. 379-385, 14th International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, California, United States, 4/03/13. https://doi.org/10.1109/ISQED.2013.6523639

System-level modelling of dynamic reconfigurable designs using functional programming abstractions. / Uchevler, B.N.; Svarstad, Kjetil; Kuper, Jan et al.

14th International Symposium on Quality Electronic Design (ISQED). Los Alamitos, CA, USA : IEEE, 2013. p. 379-385.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N1 - Conference code: 14

PY - 2013/3

Y1 - 2013/3

N2 - With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.

AB - With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.

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KW - dynamic reconfigurable designs

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KW - partial evaluation implementation technique

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KW - digital circuit verification

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KW - high-level descriptions

KW - high-level structures

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KW - Self-Reconfiguration

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BT - 14th International Symposium on Quality Electronic Design (ISQED)

PB - IEEE

CY - Los Alamitos, CA, USA

T2 - 14th International Symposium on Quality Electronic Design, ISQED 2013

Y2 - 4 March 2013 through 6 March 2013

ER -

System-level modelling of dynamic reconfigurable designs using functional programming abstractions

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