The increasing time-to-market (TTM) pressures have created the demand for rapid design of single complex chips based on reusing the design and test data. On the other hand, the availability of shrinking process technologies makes it possible to integrate a number of digital and analogue functional blocks into a single chip, mixed-signal Systemon-a-Chip (SoC). Due to the complexity of a SoC and the limited test access (lack of controllability and observability) for embedded analogue cores in the pin-limited SoC, there are a lot of technical challenges in the testing of embedded analogue cores in SoC. A hierarchical approach has been employed for testing of embedded analogue cores in our research. In this approach, the test signals for each standalone analogue core in the SoC are selected first. Next, some test translation schemes are employed to translate the corelevel test signals into system-level test signals. The research presented in this thesis deals with the system-level testing of embedded analogue cores in SoC, i.e. how to translate the core-level test patterns into system-level.
|Award date||12 Jun 2003|
|Place of Publication||Enschede, The Netherlands|
|Publication status||Published - 12 Jun 2003|