Thomas Jan Hoen* (Inventor), Yanyu Jin (Inventor), Anne J. Annema (Inventor), Jos Verlinden (Inventor)

*Corresponding author for this work

Research output: Patent


In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor formed in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.
Original languageEnglish
Patent number US20230317347A1
Priority date30/03/22
Publication statusPublished - 5 Oct 2023


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