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Tapered multipath inductors

Research output: Patent

153 Downloads (Pure)

Abstract

In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor fored in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.
Original languageEnglish
Patent numberUS 11,783,990 B1
Priority date30/03/22
Filing date30/03/22
Publication statusPublished - 10 Oct 2023

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  • Low TCL, High-Q Inductors in Standard CMOS

    Hoen, T. J., Jin, Y., Annema, A. J., Wils, N., Verlinden, J. & Nauta, B., Feb 2024, In: IEEE Microwave and Wireless Technology Letters. 34, 2, p. 179-182 4 p.

    Research output: Contribution to journalArticleAcademicpeer-review

    Open Access
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    358 Downloads (Pure)
  • Tapered multipath inductors

    Hoen, T. J. (Inventor), Jin, Y. (Inventor), Annema, A. J. (Inventor) & Verlinden, J. (Inventor), 5 Oct 2023, Patent No. US20230317347A1, Priority date 30 Mar 2022, Priority No. US202217657173A

    Research output: Patent

    Open Access

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