Template Generation and Selection Algorithms

Y. Guo, Gerardus Johannes Maria Smit, Haitze J. Broersma, P.M. Heysters

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)
62 Downloads (Pure)


The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extract functional equivalent structures, i.e. templates, from a control data flow graph. By inspecting the graph the algorithm generates all the possible templates and the corresponding matches. Using unique serial numbers and circle numbers the algorithm can find all distinct templates with multiple outputs. The template selection algorithm shows how this information can be used in compilers for reconfigurable systems. The objective of the template selection algorithm is to find an efficient cover for an application graph with a minimal number of distinct templates and minimal number of matches.
Original languageUndefined
Title of host publicationProceedings of International Workshop on System-on-Chip for Real-Time Applications 2003
EditorsW. Badaway, Y. Ismail
Place of PublicationLos Alamitos, California
Number of pages4
ISBN (Print)0-7695-1944-X
Publication statusPublished - Jun 2003
EventIWSOC: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications(IWSOC) - Calgary, Alberta, Canada
Duration: 1 Jan 1900 → …

Publication series

PublisherIEEE Computer Society


CityCalgary, Alberta, Canada
Period1/01/00 → …


  • EWI-1513
  • METIS-214812
  • IR-46374
  • CAES-EEA: Efficient Embedded Architectures

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