Temporal Logic Model Checking

Edmund M. Clarke, Ansgar Fehnker, Sumit Kumar Jha, Helmut Veith

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

Original languageEnglish
Title of host publicationHandbook of Networked and Embedded Control Systems
EditorsDimitrios Hristu-Varsakelis, William S. Levine
PublisherBirkhäuser
Pages539-558
Number of pages20
ISBN (Electronic)978-0-8176-4404-8
ISBN (Print)978-0-8176-3239-7
DOIs
Publication statusPublished - 2005
Externally publishedYes

Publication series

NameControl engineering

Cite this

Clarke, E. M., Fehnker, A., Jha, S. K., & Veith, H. (2005). Temporal Logic Model Checking. In D. Hristu-Varsakelis, & W. S. Levine (Eds.), Handbook of Networked and Embedded Control Systems (pp. 539-558). (Control engineering). Birkhäuser. https://doi.org/10.1007/0-8176-4404-0_23
Clarke, Edmund M. ; Fehnker, Ansgar ; Jha, Sumit Kumar ; Veith, Helmut. / Temporal Logic Model Checking. Handbook of Networked and Embedded Control Systems. editor / Dimitrios Hristu-Varsakelis ; William S. Levine. Birkhäuser, 2005. pp. 539-558 (Control engineering).
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Clarke, EM, Fehnker, A, Jha, SK & Veith, H 2005, Temporal Logic Model Checking. in D Hristu-Varsakelis & WS Levine (eds), Handbook of Networked and Embedded Control Systems. Control engineering, Birkhäuser, pp. 539-558. https://doi.org/10.1007/0-8176-4404-0_23

Temporal Logic Model Checking. / Clarke, Edmund M.; Fehnker, Ansgar; Jha, Sumit Kumar; Veith, Helmut.

Handbook of Networked and Embedded Control Systems. ed. / Dimitrios Hristu-Varsakelis; William S. Levine. Birkhäuser, 2005. p. 539-558 (Control engineering).

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

TY - CHAP

T1 - Temporal Logic Model Checking

AU - Clarke, Edmund M.

AU - Fehnker, Ansgar

AU - Jha, Sumit Kumar

AU - Veith, Helmut

PY - 2005

Y1 - 2005

U2 - 10.1007/0-8176-4404-0_23

DO - 10.1007/0-8176-4404-0_23

M3 - Chapter

SN - 978-0-8176-3239-7

T3 - Control engineering

SP - 539

EP - 558

BT - Handbook of Networked and Embedded Control Systems

A2 - Hristu-Varsakelis, Dimitrios

A2 - Levine, William S.

PB - Birkhäuser

ER -

Clarke EM, Fehnker A, Jha SK, Veith H. Temporal Logic Model Checking. In Hristu-Varsakelis D, Levine WS, editors, Handbook of Networked and Embedded Control Systems. Birkhäuser. 2005. p. 539-558. (Control engineering). https://doi.org/10.1007/0-8176-4404-0_23