Temporal Logic Model Checking

Edmund M. Clarke, Ansgar Fehnker, Sumit Kumar Jha, Helmut Veith

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

Original languageEnglish
Title of host publicationHandbook of Networked and Embedded Control Systems
EditorsDimitrios Hristu-Varsakelis, William S. Levine
PublisherBirkhäuser
Pages539-558
Number of pages20
ISBN (Electronic)978-0-8176-4404-8
ISBN (Print)978-0-8176-3239-7
DOIs
Publication statusPublished - 2005
Externally publishedYes

Publication series

NameControl engineering

Cite this

Clarke, E. M., Fehnker, A., Jha, S. K., & Veith, H. (2005). Temporal Logic Model Checking. In D. Hristu-Varsakelis, & W. S. Levine (Eds.), Handbook of Networked and Embedded Control Systems (pp. 539-558). (Control engineering). Birkhäuser. https://doi.org/10.1007/0-8176-4404-0_23