Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

Sandeep Kumar Goel

    Research output: ThesisPhD Thesis - Research external, graduation UT

    26 Downloads (Pure)

    Abstract

    Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins to the core should be provided. Isolation of a core is done by designing a wrapper around the core, while the test access to the core is provided by means of a dedicated Test Access Mechanism (TAM).
    Original languageEnglish
    Awarding Institution
    • University of Twente
    Supervisors/Advisors
    • Kerkhoff, Hans Gerard, Advisor
    • Krol, Th., Supervisor
    Thesis sponsors
    Award date2 Feb 2005
    Place of PublicationEindhoven
    Publisher
    Print ISBNs90-74445-65-9
    Publication statusPublished - 2 Feb 2005

    Keywords

    • METIS-226911
    • IR-48260
    • EWI-20041

    Fingerprint Dive into the research topics of 'Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips'. Together they form a unique fingerprint.

  • Cite this

    Goel, S. K. (2005). Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips. Eindhoven: Eindhoven University Press.