Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

Sandeep Kumar Goel

Research output: ThesisPhD Thesis - Research external, graduation UTAcademic

8 Downloads (Pure)

Abstract

Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins to the core should be provided. Isolation of a core is done by designing a wrapper around the core, while the test access to the core is provided by means of a dedicated Test Access Mechanism (TAM).
Original languageEnglish
Awarding Institution
  • University of Twente
Supervisors/Advisors
  • Kerkhoff, Hans G., Advisor
  • Krol, Th., Supervisor
Thesis sponsors
Award date2 Feb 2005
Place of PublicationEindhoven
Publisher
Print ISBNs90-74445-65-9
Publication statusPublished - 2 Feb 2005

Fingerprint

Scheduling
Semiconductor materials
Planning
Testing

Keywords

  • METIS-226911
  • IR-48260
  • EWI-20041

Cite this

Goel, S. K. (2005). Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips. Eindhoven: Eindhoven University Press.
Goel, Sandeep Kumar. / Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips. Eindhoven : Eindhoven University Press, 2005. 155 p.
@phdthesis{6068b0a0276c4189b085ebfc481b2148,
title = "Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips",
abstract = "Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins to the core should be provided. Isolation of a core is done by designing a wrapper around the core, while the test access to the core is provided by means of a dedicated Test Access Mechanism (TAM).",
keywords = "METIS-226911, IR-48260, EWI-20041",
author = "Goel, {Sandeep Kumar}",
year = "2005",
month = "2",
day = "2",
language = "English",
isbn = "90-74445-65-9",
publisher = "Eindhoven University Press",
school = "University of Twente",

}

Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips. / Goel, Sandeep Kumar.

Eindhoven : Eindhoven University Press, 2005. 155 p.

Research output: ThesisPhD Thesis - Research external, graduation UTAcademic

TY - THES

T1 - Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

AU - Goel, Sandeep Kumar

PY - 2005/2/2

Y1 - 2005/2/2

N2 - Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins to the core should be provided. Isolation of a core is done by designing a wrapper around the core, while the test access to the core is provided by means of a dedicated Test Access Mechanism (TAM).

AB - Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins to the core should be provided. Isolation of a core is done by designing a wrapper around the core, while the test access to the core is provided by means of a dedicated Test Access Mechanism (TAM).

KW - METIS-226911

KW - IR-48260

KW - EWI-20041

M3 - PhD Thesis - Research external, graduation UT

SN - 90-74445-65-9

PB - Eindhoven University Press

CY - Eindhoven

ER -

Goel SK. Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips. Eindhoven: Eindhoven University Press, 2005. 155 p.