Test Standards Reuse for Structured and Cost-Efficient Dependability Management of System-on-Chips

Ahmed Mohammed Youssef Ibrahim

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    132 Downloads (Pure)

    Abstract

    The continuous development in silicon manufacturing technologies and the increased reliance on design automation and IP reuse, allowed the development of complex System-on-Chips (SoCs) in order to meet the growing application processing requirements. However, the aggressive technology scaling leads to increasing lifetime dependability challenges, which might lead to huge financial and even human losses in case of safety critical applications. Therefore, addressing such challenges becomes an important design concern.

    Test standards enable a structured methodology for testing complex SoCs, and hence, they are widely used in practice with the support of design automation tools. The IEEE 1687 standard enables an efficient methodology for accessing and operating embedded instruments that are used for different purposes, such as testing, debugging, diagnosis, configuration, characterization and monitoring. A subset of such instruments are also used in dependability management, such as temperature sensors, voltage monitors, Built-In-Self-Test engines and many others. Consequently, utilizing the IEEE 1687 standard in the design of dependability management solutions for the access of embedded instruments will enable their development in a structured and cost-efficient manner, which will subsequently boost their large scale adoption.

    In this thesis, the efficient utilization of the IEEE 1687 standard in dependability management is addressed. A novel on-chip structural model for IEEE 1687 networks is devised after carefully analysing the specifications of the network construction that are described by the standard. Furthermore, the standard defines the pattern retargeting process in order to enable the reuse of the instrument operating procedures. In this thesis, pattern retargeting is performed on-chip in order to enable the reuse of dependability procedures that incorporate the operating procedures of the instruments.

    The architectural and performance requirements for dependability networks are subsequently analysed. Afterwards, architectural modifications and hierarchical network construction and management methods are introduced. Finally, an execution model for dependability procedures that use embedded instruments is proposed, by adopting two state-of-the-art execution models, and further adapting them for the usage of the IEEE 1687 standard for instrument access. The resulting execution model incorporates the modelling and retargeting methods, in addition to the network organization and architectural modifications that are proposed in this thesis.
    Original languageEnglish
    Awarding Institution
    • University of Twente
    Supervisors/Advisors
    • Kerkhoff, Hans Gerard, Supervisor
    • Smit, Gerardus Johannes Maria, Supervisor
    Award date18 Apr 2018
    Place of PublicationEnschede
    Publisher
    Print ISBNs978-90-365-4527-3
    DOIs
    Publication statusPublished - 18 Apr 2018

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    Keywords

    • Dependability
    • Functional Safety
    • IEEE 1687 Standard
    • Test Standards
    • IJTAG
    • PDL
    • ICL
    • EDA
    • Retargeting
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