Abstract
We present a MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion and inversion.
| Original language | English |
|---|---|
| Title of host publication | ICMTS 2003 |
| Subtitle of host publication | Proceedings of the 2003 International Conference on Microelectronic Test Structures : March 17-20, 2003, Double Tree Hotel, Monterey, California |
| Place of Publication | Piscataway, NJ |
| Publisher | IEEE |
| Pages | 181-185 |
| Number of pages | 5 |
| ISBN (Print) | 0-7803-7653-6 |
| DOIs | |
| Publication status | Published - 7 May 2003 |
| Event | 16th International Conference on Microelectronic Test Structures, ICMTS 2003 - Monterey, United States Duration: 17 Mar 2003 → 20 Mar 2003 Conference number: 16 http://www.homepages.ed.ac.uk/ajw/ICMTS/prog03.html |
Conference
| Conference | 16th International Conference on Microelectronic Test Structures, ICMTS 2003 |
|---|---|
| Abbreviated title | ICMTS |
| Country/Territory | United States |
| City | Monterey |
| Period | 17/03/03 → 20/03/03 |
| Internet address |
Keywords
- Integrated circuit design
- Capacitance
- CMOS integrated circuits
- Dielectric thin films
Fingerprint
Dive into the research topics of 'Test structure design considerations for RF-CV measurements on leaky dielectrics'. Together they form a unique fingerprint.Cite this
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver