In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library.
|Journal||Microprocessing and Microprogramming|
|Publication status||Published - 1993|