Testability enhancement using physical design rules in a CMOS cell library

F.C. Blom; J. Oliver; M. Rullan; C. Ferrer

doi:10.1016/0165-6074(93)90098-6

Testability enhancement using physical design rules in a CMOS cell library

F.C. Blom
, J. Oliver
, M. Rullan
, C. Ferrer

University of Twente

Research output: Contribution to journal › Article › Academic

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Abstract

In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library.

Original language	Undefined
Pages (from-to)	245-248
Journal	Microprocessing and Microprogramming
Volume	39
Issue number	2-5
DOIs	https://doi.org/10.1016/0165-6074(93)90098-6
Publication status	Published - 1993

Keywords

IR-57392

Access to Document

10.1016/0165-6074(93)90098-6

Blom93testability

Cite this

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AU - Ferrer, C.

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AB - In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library.

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U2 - 10.1016/0165-6074(93)90098-6

DO - 10.1016/0165-6074(93)90098-6

M3 - Article

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JO - Microprocessing and Microprogramming

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